422 lines
17 KiB
C
422 lines
17 KiB
C
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include "driver/spi_master.h"
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#include "soc/dport_reg.h"
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#include "soc/spi_periph.h"
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#include "rom/ets_sys.h"
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#include "esp_types.h"
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#include "esp_attr.h"
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#include "esp_intr.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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#include "esp_err.h"
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#include "soc/soc.h"
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#include "soc/dport_reg.h"
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#include "rom/lldesc.h"
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#include "driver/gpio.h"
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#include "driver/periph_ctrl.h"
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#include "esp_heap_caps.h"
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#include "driver/spi_common.h"
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#include "stdatomic.h"
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static const char *SPI_TAG = "spi";
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#define SPI_CHECK(a, str, ret_val) \
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if (!(a)) { \
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ESP_LOGE(SPI_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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return (ret_val); \
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}
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typedef struct spi_device_t spi_device_t;
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#define FUNC_SPI 1 //all pins of HSPI and VSPI shares this function number
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#define FUNC_GPIO PIN_FUNC_GPIO
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#define DMA_CHANNEL_ENABLED(dma_chan) (BIT(dma_chan-1))
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//Periph 1 is 'claimed' by SPI flash code.
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static atomic_bool spi_periph_claimed[3] = { ATOMIC_VAR_INIT(true), ATOMIC_VAR_INIT(false), ATOMIC_VAR_INIT(false)};
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static uint8_t spi_dma_chan_enabled = 0;
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static portMUX_TYPE spi_dma_spinlock = portMUX_INITIALIZER_UNLOCKED;
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//Returns true if this peripheral is successfully claimed, false if otherwise.
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bool spicommon_periph_claim(spi_host_device_t host)
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{
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bool false_var = false;
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bool ret = atomic_compare_exchange_strong(&spi_periph_claimed[host], &false_var, true);
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if (ret) periph_module_enable(spi_periph_signal[host].module);
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return ret;
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}
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//Returns true if this peripheral is successfully freed, false if otherwise.
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bool spicommon_periph_free(spi_host_device_t host)
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{
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bool true_var = true;
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bool ret = atomic_compare_exchange_strong(&spi_periph_claimed[host], &true_var, false);
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if (ret) periph_module_disable(spi_periph_signal[host].module);
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return ret;
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}
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int spicommon_irqsource_for_host(spi_host_device_t host)
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{
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return spi_periph_signal[host].irq;
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}
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spi_dev_t *spicommon_hw_for_host(spi_host_device_t host)
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{
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return spi_periph_signal[host].hw;
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}
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bool spicommon_dma_chan_claim (int dma_chan)
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{
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bool ret = false;
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assert( dma_chan == 1 || dma_chan == 2 );
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portENTER_CRITICAL(&spi_dma_spinlock);
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if ( !(spi_dma_chan_enabled & DMA_CHANNEL_ENABLED(dma_chan)) ) {
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// get the channel only when it's not claimed yet.
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spi_dma_chan_enabled |= DMA_CHANNEL_ENABLED(dma_chan);
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ret = true;
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}
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periph_module_enable( PERIPH_SPI_DMA_MODULE );
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portEXIT_CRITICAL(&spi_dma_spinlock);
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return ret;
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}
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bool spicommon_dma_chan_free(int dma_chan)
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{
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assert( dma_chan == 1 || dma_chan == 2 );
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assert( spi_dma_chan_enabled & DMA_CHANNEL_ENABLED(dma_chan) );
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portENTER_CRITICAL(&spi_dma_spinlock);
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spi_dma_chan_enabled &= ~DMA_CHANNEL_ENABLED(dma_chan);
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if ( spi_dma_chan_enabled == 0 ) {
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//disable the DMA only when all the channels are freed.
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periph_module_disable( PERIPH_SPI_DMA_MODULE );
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}
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portEXIT_CRITICAL(&spi_dma_spinlock);
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return true;
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}
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/*
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Do the common stuff to hook up a SPI host to a bus defined by a bunch of GPIO pins. Feed it a host number and a
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bus config struct and it'll set up the GPIO matrix and enable the device. If a pin is set to non-negative value,
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it should be able to be initialized.
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*/
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esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, int dma_chan, uint32_t flags, uint32_t* flags_o)
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{
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bool use_iomux = true;
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uint32_t temp_flag=0;
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bool quad_pins_exist = true;
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//the MISO should be output capable in slave mode, or in DIO/QIO mode.
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bool miso_output = !(flags&SPICOMMON_BUSFLAG_MASTER) || flags&SPICOMMON_BUSFLAG_DUAL;
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//the MOSI should be output capble in master mode, or in DIO/QIO mode.
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bool mosi_output = (flags&SPICOMMON_BUSFLAG_MASTER)!=0 || flags&SPICOMMON_BUSFLAG_DUAL;
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//check pins existence and if the selected pins correspond to the iomux pins of the peripheral
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if (bus_config->sclk_io_num>=0) {
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temp_flag |= SPICOMMON_BUSFLAG_SCLK;
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SPI_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(bus_config->sclk_io_num), "sclk not valid", ESP_ERR_INVALID_ARG);
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if (bus_config->sclk_io_num != spi_periph_signal[host].spiclk_iomux_pin) use_iomux = false;
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} else {
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SPI_CHECK((flags&SPICOMMON_BUSFLAG_SCLK)==0, "sclk pin required.", ESP_ERR_INVALID_ARG);
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}
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if (bus_config->quadwp_io_num>=0) {
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SPI_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(bus_config->quadwp_io_num), "spiwp not valid", ESP_ERR_INVALID_ARG);
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if (bus_config->quadwp_io_num != spi_periph_signal[host].spiwp_iomux_pin) use_iomux = false;
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} else {
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quad_pins_exist = false;
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SPI_CHECK((flags&SPICOMMON_BUSFLAG_WPHD)==0, "spiwp pin required.", ESP_ERR_INVALID_ARG);
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}
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if (bus_config->quadhd_io_num>=0) {
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SPI_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(bus_config->quadhd_io_num), "spihd not valid", ESP_ERR_INVALID_ARG);
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if (bus_config->quadhd_io_num != spi_periph_signal[host].spihd_iomux_pin) use_iomux = false;
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} else {
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quad_pins_exist = false;
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SPI_CHECK((flags&SPICOMMON_BUSFLAG_WPHD)==0, "spihd pin required.", ESP_ERR_INVALID_ARG);
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}
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if (bus_config->mosi_io_num >= 0) {
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temp_flag |= SPICOMMON_BUSFLAG_MOSI;
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if (mosi_output) {
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SPI_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(bus_config->mosi_io_num), "mosi not valid", ESP_ERR_INVALID_ARG);
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} else {
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SPI_CHECK(GPIO_IS_VALID_GPIO(bus_config->mosi_io_num), "mosi not valid", ESP_ERR_INVALID_ARG);
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}
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if (bus_config->mosi_io_num != spi_periph_signal[host].spid_iomux_pin) use_iomux = false;
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} else {
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SPI_CHECK((flags&SPICOMMON_BUSFLAG_MOSI)==0, "mosi pin required.", ESP_ERR_INVALID_ARG);
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}
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if (bus_config->miso_io_num>=0) {
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temp_flag |= SPICOMMON_BUSFLAG_MISO;
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if (miso_output) {
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SPI_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(bus_config->miso_io_num), "miso not valid", ESP_ERR_INVALID_ARG);
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} else {
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SPI_CHECK(GPIO_IS_VALID_GPIO(bus_config->miso_io_num), "miso not valid", ESP_ERR_INVALID_ARG);
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}
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if (bus_config->miso_io_num != spi_periph_signal[host].spiq_iomux_pin) use_iomux = false;
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} else {
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SPI_CHECK((flags&SPICOMMON_BUSFLAG_MISO)==0, "miso pin required.", ESP_ERR_INVALID_ARG);
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}
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//set flags for DUAL mode according to output-capability of MOSI and MISO pins.
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if ( (bus_config->mosi_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->mosi_io_num)) &&
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(bus_config->miso_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->miso_io_num)) ) {
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temp_flag |= SPICOMMON_BUSFLAG_DUAL;
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}
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//set flags for QUAD mode according to the existence of wp and hd
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if (quad_pins_exist) temp_flag |= SPICOMMON_BUSFLAG_WPHD;
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//check iomux pins if required.
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SPI_CHECK((flags&SPICOMMON_BUSFLAG_NATIVE_PINS)==0 || use_iomux, "not using iomux pins", ESP_ERR_INVALID_ARG);
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if (use_iomux) {
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//All SPI iomux pin selections resolve to 1, so we put that here instead of trying to figure
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//out which FUNC_GPIOx_xSPIxx to grab; they all are defined to 1 anyway.
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ESP_LOGD(SPI_TAG, "SPI%d use iomux pins.", host );
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if (bus_config->mosi_io_num >= 0) {
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gpio_iomux_in(bus_config->mosi_io_num, spi_periph_signal[host].spid_in);
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gpio_iomux_out(bus_config->mosi_io_num, FUNC_SPI, false);
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}
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if (bus_config->miso_io_num >= 0) {
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gpio_iomux_in(bus_config->miso_io_num, spi_periph_signal[host].spiq_in);
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gpio_iomux_out(bus_config->miso_io_num, FUNC_SPI, false);
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}
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if (bus_config->quadwp_io_num >= 0) {
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gpio_iomux_in(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_in);
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gpio_iomux_out(bus_config->quadwp_io_num, FUNC_SPI, false);
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}
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if (bus_config->quadhd_io_num >= 0) {
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gpio_iomux_in(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_in);
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gpio_iomux_out(bus_config->quadhd_io_num, FUNC_SPI, false);
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}
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if (bus_config->sclk_io_num >= 0) {
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gpio_iomux_in(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_in);
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gpio_iomux_out(bus_config->sclk_io_num, FUNC_SPI, false);
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}
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temp_flag |= SPICOMMON_BUSFLAG_NATIVE_PINS;
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} else {
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//Use GPIO matrix
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ESP_LOGD(SPI_TAG, "SPI%d use gpio matrix.", host );
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if (bus_config->mosi_io_num >= 0) {
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if (mosi_output || (temp_flag&SPICOMMON_BUSFLAG_DUAL)) {
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gpio_set_direction(bus_config->mosi_io_num, GPIO_MODE_INPUT_OUTPUT);
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gpio_matrix_out(bus_config->mosi_io_num, spi_periph_signal[host].spid_out, false, false);
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} else {
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gpio_set_direction(bus_config->mosi_io_num, GPIO_MODE_INPUT);
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}
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gpio_matrix_in(bus_config->mosi_io_num, spi_periph_signal[host].spid_in, false);
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], FUNC_GPIO);
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}
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if (bus_config->miso_io_num >= 0) {
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if (miso_output || (temp_flag&SPICOMMON_BUSFLAG_DUAL)) {
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gpio_set_direction(bus_config->miso_io_num, GPIO_MODE_INPUT_OUTPUT);
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gpio_matrix_out(bus_config->miso_io_num, spi_periph_signal[host].spiq_out, false, false);
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} else {
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gpio_set_direction(bus_config->miso_io_num, GPIO_MODE_INPUT);
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}
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gpio_matrix_in(bus_config->miso_io_num, spi_periph_signal[host].spiq_in, false);
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->miso_io_num], FUNC_GPIO);
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}
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if (bus_config->quadwp_io_num >= 0) {
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gpio_set_direction(bus_config->quadwp_io_num, GPIO_MODE_INPUT_OUTPUT);
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gpio_matrix_out(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_out, false, false);
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gpio_matrix_in(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_in, false);
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], FUNC_GPIO);
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}
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if (bus_config->quadhd_io_num >= 0) {
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gpio_set_direction(bus_config->quadhd_io_num, GPIO_MODE_INPUT_OUTPUT);
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gpio_matrix_out(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_out, false, false);
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gpio_matrix_in(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_in, false);
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], FUNC_GPIO);
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}
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if (bus_config->sclk_io_num >= 0) {
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gpio_set_direction(bus_config->sclk_io_num, GPIO_MODE_INPUT_OUTPUT);
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gpio_matrix_out(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_out, false, false);
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gpio_matrix_in(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_in, false);
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], FUNC_GPIO);
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}
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}
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//Select DMA channel.
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DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2));
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if (flags_o) *flags_o = temp_flag;
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return ESP_OK;
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}
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//Find any pin with output muxed to ``func`` and reset it to GPIO
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static void reset_func_to_gpio(int func)
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{
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for (int x = 0; x < GPIO_PIN_COUNT; x++) {
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if (GPIO_IS_VALID_GPIO(x) && (READ_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG + (x * 4))&GPIO_FUNC0_OUT_SEL_M) == func) {
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gpio_matrix_out(x, SIG_GPIO_OUT_IDX, false, false);
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}
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}
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}
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esp_err_t spicommon_bus_free_io(spi_host_device_t host)
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{
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if (REG_GET_FIELD(GPIO_PIN_MUX_REG[spi_periph_signal[host].spid_iomux_pin], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[spi_periph_signal[host].spid_iomux_pin], PIN_FUNC_GPIO);
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if (REG_GET_FIELD(GPIO_PIN_MUX_REG[spi_periph_signal[host].spiq_iomux_pin], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[spi_periph_signal[host].spiq_iomux_pin], PIN_FUNC_GPIO);
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if (REG_GET_FIELD(GPIO_PIN_MUX_REG[spi_periph_signal[host].spiclk_iomux_pin], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[spi_periph_signal[host].spiclk_iomux_pin], PIN_FUNC_GPIO);
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if (REG_GET_FIELD(GPIO_PIN_MUX_REG[spi_periph_signal[host].spiwp_iomux_pin], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[spi_periph_signal[host].spiwp_iomux_pin], PIN_FUNC_GPIO);
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if (REG_GET_FIELD(GPIO_PIN_MUX_REG[spi_periph_signal[host].spihd_iomux_pin], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[spi_periph_signal[host].spihd_iomux_pin], PIN_FUNC_GPIO);
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reset_func_to_gpio(spi_periph_signal[host].spid_out);
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reset_func_to_gpio(spi_periph_signal[host].spiq_out);
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reset_func_to_gpio(spi_periph_signal[host].spiclk_out);
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reset_func_to_gpio(spi_periph_signal[host].spiwp_out);
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reset_func_to_gpio(spi_periph_signal[host].spihd_out);
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return ESP_OK;
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}
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esp_err_t spicommon_bus_free_io_cfg(const spi_bus_config_t *bus_cfg)
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{
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int pin_array[] = {
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bus_cfg->mosi_io_num,
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bus_cfg->miso_io_num,
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bus_cfg->sclk_io_num,
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bus_cfg->quadwp_io_num,
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bus_cfg->quadhd_io_num,
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};
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for (int i = 0; i < sizeof(pin_array)/sizeof(int); i ++) {
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const int io = pin_array[i];
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if (io >= 0 && GPIO_IS_VALID_GPIO(io)) gpio_reset_pin(io);
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}
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return ESP_OK;
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}
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void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, int force_gpio_matrix)
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{
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if (!force_gpio_matrix && cs_io_num == spi_periph_signal[host].spics0_iomux_pin && cs_num == 0) {
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//The cs0s for all SPI peripherals map to pin mux source 1, so we use that instead of a define.
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gpio_iomux_in(cs_io_num, spi_periph_signal[host].spics_in);
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gpio_iomux_out(cs_io_num, FUNC_SPI, false);
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} else {
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//Use GPIO matrix
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gpio_matrix_out(cs_io_num, spi_periph_signal[host].spics_out[cs_num], false, false);
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if (cs_num == 0) gpio_matrix_in(cs_io_num, spi_periph_signal[host].spics_in, false);
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cs_io_num], FUNC_GPIO);
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}
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}
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void spicommon_cs_free(spi_host_device_t host, int cs_io_num)
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{
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if (cs_io_num == 0 && REG_GET_FIELD(GPIO_PIN_MUX_REG[spi_periph_signal[host].spics0_iomux_pin], MCU_SEL) == 1) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[spi_periph_signal[host].spics0_iomux_pin], PIN_FUNC_GPIO);
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}
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reset_func_to_gpio(spi_periph_signal[host].spics_out[cs_io_num]);
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}
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void spicommon_cs_free_io(int cs_gpio_num)
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{
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assert(cs_gpio_num>=0 && GPIO_IS_VALID_GPIO(cs_gpio_num));
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gpio_reset_pin(cs_gpio_num);
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}
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//Set up a list of dma descriptors. dmadesc is an array of descriptors. Data is the buffer to point to.
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void IRAM_ATTR spicommon_setup_dma_desc_links(lldesc_t *dmadesc, int len, const uint8_t *data, bool isrx)
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{
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int n = 0;
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while (len) {
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int dmachunklen = len;
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if (dmachunklen > SPI_MAX_DMA_LEN) dmachunklen = SPI_MAX_DMA_LEN;
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if (isrx) {
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//Receive needs DMA length rounded to next 32-bit boundary
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dmadesc[n].size = (dmachunklen + 3) & (~3);
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dmadesc[n].length = (dmachunklen + 3) & (~3);
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} else {
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dmadesc[n].size = dmachunklen;
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dmadesc[n].length = dmachunklen;
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}
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dmadesc[n].buf = (uint8_t *)data;
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dmadesc[n].eof = 0;
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dmadesc[n].sosf = 0;
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dmadesc[n].owner = 1;
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dmadesc[n].qe.stqe_next = &dmadesc[n + 1];
|
|
len -= dmachunklen;
|
|
data += dmachunklen;
|
|
n++;
|
|
}
|
|
dmadesc[n - 1].eof = 1; //Mark last DMA desc as end of stream.
|
|
dmadesc[n - 1].qe.stqe_next = NULL;
|
|
}
|
|
|
|
|
|
/*
|
|
Code for workaround for DMA issue in ESP32 v0/v1 silicon
|
|
*/
|
|
|
|
|
|
static volatile int dmaworkaround_channels_busy[2] = {0, 0};
|
|
static dmaworkaround_cb_t dmaworkaround_cb;
|
|
static void *dmaworkaround_cb_arg;
|
|
static portMUX_TYPE dmaworkaround_mux = portMUX_INITIALIZER_UNLOCKED;
|
|
static int dmaworkaround_waiting_for_chan = 0;
|
|
|
|
bool IRAM_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t cb, void *arg)
|
|
{
|
|
int otherchan = (dmachan == 1) ? 2 : 1;
|
|
bool ret;
|
|
portENTER_CRITICAL_ISR(&dmaworkaround_mux);
|
|
if (dmaworkaround_channels_busy[otherchan-1]) {
|
|
//Other channel is busy. Call back when it's done.
|
|
dmaworkaround_cb = cb;
|
|
dmaworkaround_cb_arg = arg;
|
|
dmaworkaround_waiting_for_chan = otherchan;
|
|
ret = false;
|
|
} else {
|
|
//Reset DMA
|
|
periph_module_reset( PERIPH_SPI_DMA_MODULE );
|
|
ret = true;
|
|
}
|
|
portEXIT_CRITICAL_ISR(&dmaworkaround_mux);
|
|
return ret;
|
|
}
|
|
|
|
bool IRAM_ATTR spicommon_dmaworkaround_reset_in_progress()
|
|
{
|
|
return (dmaworkaround_waiting_for_chan != 0);
|
|
}
|
|
|
|
void IRAM_ATTR spicommon_dmaworkaround_idle(int dmachan)
|
|
{
|
|
portENTER_CRITICAL_ISR(&dmaworkaround_mux);
|
|
dmaworkaround_channels_busy[dmachan-1] = 0;
|
|
if (dmaworkaround_waiting_for_chan == dmachan) {
|
|
//Reset DMA
|
|
periph_module_reset( PERIPH_SPI_DMA_MODULE );
|
|
dmaworkaround_waiting_for_chan = 0;
|
|
//Call callback
|
|
dmaworkaround_cb(dmaworkaround_cb_arg);
|
|
|
|
}
|
|
portEXIT_CRITICAL_ISR(&dmaworkaround_mux);
|
|
}
|
|
|
|
void IRAM_ATTR spicommon_dmaworkaround_transfer_active(int dmachan)
|
|
{
|
|
portENTER_CRITICAL_ISR(&dmaworkaround_mux);
|
|
dmaworkaround_channels_busy[dmachan-1] = 1;
|
|
portEXIT_CRITICAL_ISR(&dmaworkaround_mux);
|
|
}
|
|
|
|
|