308 lines
11 KiB
C
308 lines
11 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stddef.h>
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#include <stdint.h>
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#include "flash_qio_mode.h"
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#include "esp_log.h"
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#include "esp_err.h"
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#include "rom/spi_flash.h"
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#include "rom/efuse.h"
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#include "soc/spi_struct.h"
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#include "soc/efuse_reg.h"
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#include "sdkconfig.h"
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/* SPI flash controller */
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#define SPIFLASH SPI1
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/* SPI commands (actual on-wire commands not SPI controller bitmasks)
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Suitable for use with the execute_flash_command static function.
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*/
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#define CMD_RDID 0x9F
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#define CMD_WRSR 0x01
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#define CMD_WRSR2 0x31 /* Not all SPI flash uses this command */
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#define CMD_WREN 0x06
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#define CMD_WRDI 0x04
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#define CMD_RDSR 0x05
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#define CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
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#define CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */
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static const char *TAG = "qio_mode";
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typedef unsigned (*read_status_fn_t)();
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typedef void (*write_status_fn_t)(unsigned);
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typedef struct __attribute__((packed)) {
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const char *manufacturer;
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uint8_t mfg_id; /* 8-bit JEDEC manufacturer ID */
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uint16_t flash_id; /* 16-bit JEDEC flash chip ID */
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uint16_t id_mask; /* Bits to match on in flash chip ID */
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read_status_fn_t read_status_fn;
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write_status_fn_t write_status_fn;
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uint8_t status_qio_bit;
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} qio_info_t;
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/* Read 8 bit status using RDSR command */
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static unsigned read_status_8b_rdsr();
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/* Read 8 bit status (second byte) using RDSR2 command */
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static unsigned read_status_8b_rdsr2();
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/* read 16 bit status using RDSR & RDSR2 (low and high bytes) */
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static unsigned read_status_16b_rdsr_rdsr2();
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/* Write 8 bit status using WRSR */
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static void write_status_8b_wrsr(unsigned new_status);
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/* Write 8 bit status (second byte) using WRSR2 */
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static void write_status_8b_wrsr2(unsigned new_status);
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/* Write 16 bit status using WRSR */
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static void write_status_16b_wrsr(unsigned new_status);
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/* Read 8 bit status of XM25QU64A */
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static unsigned read_status_8b_xmc25qu64a();
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/* Write 8 bit status of XM25QU64A */
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static void write_status_8b_xmc25qu64a(unsigned new_status);
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#define ESP32_D2WD_WP_GPIO 7 /* ESP32-D2WD has this GPIO wired to WP pin of flash */
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#ifndef CONFIG_BOOTLOADER_SPI_WP_PIN // Set in menuconfig if SPI flasher config is set to a quad mode
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#define CONFIG_BOOTLOADER_SPI_WP_PIN ESP32_D2WD_WP_GPIO
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#endif
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/* Array of known flash chips and data to enable Quad I/O mode
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Manufacturer & flash ID can be tested by running "esptool.py
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flash_id"
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If manufacturer ID matches, and flash ID ORed with flash ID mask
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matches, enable_qio_mode() will execute "Read Cmd", test if bit
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number "QIE Bit" is set, and if not set it will call "Write Cmd"
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with this bit set.
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Searching of this table stops when the first match is found.
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*/
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const static qio_info_t chip_data[] = {
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/* Manufacturer, mfg_id, flash_id, id mask, Read Status, Write Status, QIE Bit */
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{ "MXIC", 0xC2, 0x2000, 0xFF00, read_status_8b_rdsr, write_status_8b_wrsr, 6 },
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{ "ISSI", 0x9D, 0x4000, 0xCF00, read_status_8b_rdsr, write_status_8b_wrsr, 6 }, /* IDs 0x40xx, 0x70xx */
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{ "WinBond", 0xEF, 0x4000, 0xFF00, read_status_16b_rdsr_rdsr2, write_status_16b_wrsr, 9 },
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{ "GD", 0xC8, 0x6000, 0xFF00, read_status_16b_rdsr_rdsr2, write_status_16b_wrsr, 9 },
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{ "XM25QU64A", 0x20, 0x3817, 0xFFFF, read_status_8b_xmc25qu64a, write_status_8b_xmc25qu64a, 6 },
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/* Final entry is default entry, if no other IDs have matched.
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This approach works for chips including:
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GigaDevice (mfg ID 0xC8, flash IDs including 4016),
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FM25Q32 (QOUT mode only, mfg ID 0xA1, flash IDs including 4016)
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*/
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{ NULL, 0xFF, 0xFFFF, 0xFFFF, read_status_8b_rdsr2, write_status_8b_wrsr2, 1 },
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};
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#define NUM_CHIPS (sizeof(chip_data) / sizeof(qio_info_t))
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static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
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write_status_fn_t write_status_fn,
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uint8_t status_qio_bit);
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/* Generic function to use the "user command" SPI controller functionality
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to send commands to the SPI flash and read the respopnse.
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The command passed here is always the on-the-wire command given to the SPI flash unit.
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*/
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static uint32_t execute_flash_command(uint8_t command, uint32_t mosi_data, uint8_t mosi_len, uint8_t miso_len);
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/* dummy_len_plus values defined in ROM for SPI flash configuration */
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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uint32_t bootloader_read_flash_id()
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{
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uint32_t id = execute_flash_command(CMD_RDID, 0, 0, 24);
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id = ((id & 0xff) << 16) | ((id >> 16) & 0xff) | (id & 0xff00);
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return id;
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}
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void bootloader_enable_qio_mode(void)
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{
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uint32_t raw_flash_id;
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uint8_t mfg_id;
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uint16_t flash_id;
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int i;
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ESP_LOGD(TAG, "Probing for QIO mode enable...");
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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raw_flash_id = g_rom_flashchip.device_id;
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ESP_LOGD(TAG, "Raw SPI flash chip id 0x%x", raw_flash_id);
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mfg_id = (raw_flash_id >> 16) & 0xFF;
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flash_id = raw_flash_id & 0xFFFF;
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ESP_LOGD(TAG, "Manufacturer ID 0x%02x chip ID 0x%04x", mfg_id, flash_id);
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for (i = 0; i < NUM_CHIPS-1; i++) {
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const qio_info_t *chip = &chip_data[i];
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if (mfg_id == chip->mfg_id && (flash_id & chip->id_mask) == (chip->flash_id & chip->id_mask)) {
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ESP_LOGI(TAG, "Enabling QIO for flash chip %s", chip_data[i].manufacturer);
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break;
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}
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}
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if (i == NUM_CHIPS - 1) {
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ESP_LOGI(TAG, "Enabling default flash chip QIO");
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}
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enable_qio_mode(chip_data[i].read_status_fn,
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chip_data[i].write_status_fn,
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chip_data[i].status_qio_bit);
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}
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static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
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write_status_fn_t write_status_fn,
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uint8_t status_qio_bit)
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{
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uint32_t status;
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
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if (spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) {
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// spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP,
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// which is compiled into the bootloader instead.
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//
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// Most commonly an overriden pin mapping means ESP32-D2WD or ESP32-PICOD4.
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//Warn if chip is ESP32-D2WD/ESP32-PICOD4 but someone has changed the WP pin
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//assignment from that chip's WP pin.
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uint32_t pkg_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
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if (CONFIG_BOOTLOADER_SPI_WP_PIN != ESP32_D2WD_WP_GPIO &&
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(pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
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pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
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pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
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ESP_LOGW(TAG, "Chip is ESP32-D2WD/ESP32-PICOD4 but flash WP pin is different value to internal flash");
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}
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}
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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status = read_status_fn();
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ESP_LOGD(TAG, "Initial flash chip status 0x%x", status);
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if ((status & (1<<status_qio_bit)) == 0) {
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execute_flash_command(CMD_WREN, 0, 0, 0);
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write_status_fn(status | (1<<status_qio_bit));
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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status = read_status_fn();
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ESP_LOGD(TAG, "Updated flash chip status 0x%x", status);
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if ((status & (1<<status_qio_bit)) == 0) {
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ESP_LOGE(TAG, "Failed to set QIE bit, not enabling QIO mode");
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return ESP_FAIL;
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}
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} else {
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ESP_LOGD(TAG, "QIO mode already enabled in flash");
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}
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ESP_LOGD(TAG, "Enabling QIO mode...");
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esp_rom_spiflash_read_mode_t mode;
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#if CONFIG_FLASHMODE_QOUT
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mode = ESP_ROM_SPIFLASH_QOUT_MODE;
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#else
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mode = ESP_ROM_SPIFLASH_QIO_MODE;
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#endif
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esp_rom_spiflash_config_readmode(mode);
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esp_rom_spiflash_select_qio_pins(CONFIG_BOOTLOADER_SPI_WP_PIN, spiconfig);
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return ESP_OK;
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}
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static unsigned read_status_8b_rdsr()
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{
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return execute_flash_command(CMD_RDSR, 0, 0, 8);
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}
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static unsigned read_status_8b_rdsr2()
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{
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return execute_flash_command(CMD_RDSR2, 0, 0, 8);
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}
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static unsigned read_status_16b_rdsr_rdsr2()
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{
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return execute_flash_command(CMD_RDSR, 0, 0, 8) | (execute_flash_command(CMD_RDSR2, 0, 0, 8) << 8);
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}
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static void write_status_8b_wrsr(unsigned new_status)
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{
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execute_flash_command(CMD_WRSR, new_status, 8, 0);
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}
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static void write_status_8b_wrsr2(unsigned new_status)
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{
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execute_flash_command(CMD_WRSR2, new_status, 8, 0);
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}
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static void write_status_16b_wrsr(unsigned new_status)
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{
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execute_flash_command(CMD_WRSR, new_status, 16, 0);
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}
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static unsigned read_status_8b_xmc25qu64a()
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{
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execute_flash_command(CMD_OTPEN, 0, 0, 0); /* Enter OTP mode */
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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uint32_t read_status = execute_flash_command(CMD_RDSR, 0, 0, 8);
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execute_flash_command(CMD_WRDI, 0, 0, 0); /* Exit OTP mode */
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return read_status;
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}
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static void write_status_8b_xmc25qu64a(unsigned new_status)
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{
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execute_flash_command(CMD_OTPEN, 0, 0, 0); /* Enter OTP mode */
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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execute_flash_command(CMD_WRSR, new_status, 8, 0);
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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execute_flash_command(CMD_WRDI, 0, 0, 0); /* Exit OTP mode */
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}
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static uint32_t execute_flash_command(uint8_t command, uint32_t mosi_data, uint8_t mosi_len, uint8_t miso_len)
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{
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uint32_t old_ctrl_reg = SPIFLASH.ctrl.val;
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SPIFLASH.ctrl.val = SPI_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
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SPIFLASH.user.usr_dummy = 0;
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SPIFLASH.user.usr_addr = 0;
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SPIFLASH.user.usr_command = 1;
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SPIFLASH.user2.usr_command_bitlen = 7;
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SPIFLASH.user2.usr_command_value = command;
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SPIFLASH.user.usr_miso = miso_len > 0;
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SPIFLASH.miso_dlen.usr_miso_dbitlen = miso_len ? (miso_len - 1) : 0;
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SPIFLASH.user.usr_mosi = mosi_len > 0;
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SPIFLASH.mosi_dlen.usr_mosi_dbitlen = mosi_len ? (mosi_len - 1) : 0;
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SPIFLASH.data_buf[0] = mosi_data;
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if (g_rom_spiflash_dummy_len_plus[1]) {
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/* When flash pins are mapped via GPIO matrix, need a dummy cycle before reading via MISO */
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if (miso_len > 0) {
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SPIFLASH.user.usr_dummy = 1;
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SPIFLASH.user1.usr_dummy_cyclelen = g_rom_spiflash_dummy_len_plus[1] - 1;
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} else {
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SPIFLASH.user.usr_dummy = 0;
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SPIFLASH.user1.usr_dummy_cyclelen = 0;
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}
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}
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SPIFLASH.cmd.usr = 1;
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while(SPIFLASH.cmd.usr != 0)
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{ }
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SPIFLASH.ctrl.val = old_ctrl_reg;
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return SPIFLASH.data_buf[0];
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}
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