884 lines
26 KiB
C
884 lines
26 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*******************************************************************************
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* NOTICE
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* The hal is not public api, don't use in application code.
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* See readme.md in soc/include/hal/readme.md
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******************************************************************************/
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// The LL layer for ESP32-S2 SPI register operations
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#pragma once
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#include <stdlib.h> //for abs()
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#include <string.h>
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#include "hal/hal_defs.h"
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#include "esp_types.h"
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#include "soc/spi_periph.h"
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#include "esp32s2/rom/lldesc.h"
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/// Registers to reset during initialization. Don't use in app.
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#define SPI_LL_RST_MASK (SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST)
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/// Interrupt not used. Don't use in app.
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#define SPI_LL_UNUSED_INT_MASK (SPI_INT_TRANS_DONE_EN | SPI_INT_WR_DMA_DONE_EN | SPI_INT_RD_DMA_DONE_EN | SPI_INT_WR_BUF_DONE_EN | SPI_INT_RD_BUF_DONE_EN)
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/// Swap the bit order to its correct place to send
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#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
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#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : &GPSPI3))
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/**
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* The data structure holding calculated clock configuration. Since the
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* calculation needs long time, it should be calculated during initialization and
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* stored somewhere to be quickly used.
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*/
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typedef uint32_t spi_ll_clock_val_t;
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/** IO modes supported by the master. */
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typedef enum {
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SPI_LL_IO_MODE_NORMAL = 0, ///< 1-bit mode for all phases
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SPI_LL_IO_MODE_DIO, ///< 2-bit mode for address and data phases, 1-bit mode for command phase
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SPI_LL_IO_MODE_DUAL, ///< 2-bit mode for data phases only, 1-bit mode for command and address phases
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SPI_LL_IO_MODE_QIO, ///< 4-bit mode for address and data phases, 1-bit mode for command phase
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SPI_LL_IO_MODE_QUAD, ///< 4-bit mode for data phases only, 1-bit mode for command and address phases
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} spi_ll_io_mode_t;
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/// Interrupt type for different working pattern
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typedef enum {
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SPI_LL_INT_TYPE_NORMAL = 0, ///< Typical pattern, only wait for trans done
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SPI_LL_INT_TYPE_SEG = 1, ///< Wait for DMA signals
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} spi_ll_slave_intr_type;
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/*------------------------------------------------------------------------------
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* Control
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*----------------------------------------------------------------------------*/
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/**
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* Initialize SPI peripheral (master).
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_master_init(spi_dev_t *hw)
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{
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//Reset DMA
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hw->dma_conf.val |= SPI_LL_RST_MASK;
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hw->dma_out_link.start = 0;
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hw->dma_in_link.start = 0;
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hw->dma_conf.val &= ~SPI_LL_RST_MASK;
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//Reset timing
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hw->ctrl2.val = 0;
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//use all 64 bytes of the buffer
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hw->user.usr_miso_highpart = 0;
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hw->user.usr_mosi_highpart = 0;
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//Disable unneeded ints
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hw->slave.val &= ~SPI_LL_UNUSED_INT_MASK;
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//disable a feature may cause transaction to be too long
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hw->user.usr_prep_hold = 0;
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}
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/**
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* Initialize SPI peripheral (slave).
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_slave_init(spi_dev_t *hw)
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{
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//it's stupid, but if something goes wrong, try to uncomment it
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//hw->slave.slave_mode = 1;
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//Configure slave
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hw->clock.val = 0;
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hw->user.val = 0;
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hw->ctrl.val = 0;
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hw->user.doutdin = 1; //we only support full duplex
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hw->user.sio = 0;
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hw->user.tx_start_bit = 7;
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hw->slave.slave_mode = 1;
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hw->dma_conf.val |= SPI_LL_RST_MASK;
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hw->dma_out_link.start = 0;
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hw->dma_in_link.start = 0;
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hw->dma_conf.val &= ~SPI_LL_RST_MASK;
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hw->slave.sync_reset = 1;
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hw->slave.sync_reset = 0;
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//use all 64 bytes of the buffer
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hw->user.usr_miso_highpart = 0;
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hw->user.usr_mosi_highpart = 0;
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//by default seg mode is disabled
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hw->dma_conf.dma_continue = 0;
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//Disable unneeded ints
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hw->slave.val &= ~SPI_LL_UNUSED_INT_MASK;
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hw->dma_int_ena.val = 0;
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}
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/**
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* Reset TX and RX DMAs.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_reset_dma(spi_dev_t *hw)
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{
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//Reset DMA peripheral
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hw->dma_conf.val |= SPI_LL_RST_MASK;
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hw->dma_out_link.start = 0;
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hw->dma_in_link.start = 0;
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hw->dma_conf.val &= ~SPI_LL_RST_MASK;
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hw->dma_conf.out_data_burst_en = 1;
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hw->dma_conf.indscr_burst_en = 1;
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hw->dma_conf.outdscr_burst_en = 1;
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hw->dma_in_link.dma_rx_ena = 0;
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assert(hw->dma_in_link.dma_rx_ena == 0);
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}
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/**
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* Start RX DMA.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param addr Address of the beginning DMA descriptor.
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*/
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static inline void spi_ll_rxdma_start(spi_dev_t *hw, lldesc_t *addr)
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{
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//if something breaks, uncomment this line
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//hw->dma_in_link.restart = 1;
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hw->dma_in_link.addr = (int) addr & 0xFFFFF;
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hw->dma_in_link.start = 1;
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}
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/**
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* Start TX DMA.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param addr Address of the beginning DMA descriptor.
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*/
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static inline void spi_ll_txdma_start(spi_dev_t *hw, lldesc_t *addr)
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{
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//if something breaks, uncomment this line
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hw->dma_out_link.restart = 1;
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hw->dma_out_link.addr = (int) addr & 0xFFFFF;
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hw->dma_out_link.start = 1;
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}
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/**
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* Write to SPI buffer.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param buffer_to_send Data address to copy to the buffer.
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* @param bitlen Length to copy, in bits.
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*/
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static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen)
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{
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for (int x = 0; x < bitlen; x += 32) {
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//Use memcpy to get around alignment issues for txdata
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uint32_t word;
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memcpy(&word, &buffer_to_send[x / 8], 4);
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hw->data_buf[(x / 32)] = word;
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}
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}
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/**
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* Read from SPI buffer.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param buffer_to_rcv Address to copy buffer data to.
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* @param bitlen Length to copy, in bits.
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*/
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static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen)
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{
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for (int x = 0; x < bitlen; x += 32) {
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//Do a memcpy to get around possible alignment issues in rx_buffer
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uint32_t word = hw->data_buf[x / 32];
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int len = bitlen - x;
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if (len > 32) {
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len = 32;
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}
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memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8);
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}
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}
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/**
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* Check whether user-defined transaction is done.
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*
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* @param hw Beginning address of the peripheral registers.
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*
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* @return true if transaction is done, otherwise false.
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*/
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static inline bool spi_ll_usr_is_done(spi_dev_t *hw)
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{
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return hw->slave.trans_done;
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}
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/**
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* Trigger start of user-defined transaction.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_user_start(spi_dev_t *hw)
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{
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hw->cmd.usr = 1;
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}
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/**
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* Get current running command bit-mask. (Preview)
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*
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* @param hw Beginning address of the peripheral registers.
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*
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* @return Bitmask of running command, see ``SPI_CMD_REG``. 0 if no in-flight command.
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*/
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static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw)
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{
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return hw->cmd.val;
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}
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/**
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* Disable the trans_done interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_disable_int(spi_dev_t *hw)
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{
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hw->slave.trans_inten = 0;
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}
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/**
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* Clear the trans_done interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_clear_int_stat(spi_dev_t *hw)
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{
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hw->slave.trans_done = 0;
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hw->dma_int_clr.val = UINT32_MAX;
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}
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/**
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* Set the trans_done interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_set_int_stat(spi_dev_t *hw)
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{
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hw->slave.trans_done = 1;
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}
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/**
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* Enable the trans_done interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_enable_int(spi_dev_t *hw)
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{
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hw->slave.trans_inten = 1;
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}
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/**
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* Set different interrupt types for the slave.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param int_type Interrupt type
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*/
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static inline void spi_ll_slave_set_int_type(spi_dev_t *hw, spi_ll_slave_intr_type int_type)
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{
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switch (int_type) {
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case SPI_LL_INT_TYPE_SEG:
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hw->dma_int_ena.in_suc_eof = 1;
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hw->dma_int_ena.out_total_eof = 1;
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hw->slave.trans_inten = 0;
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break;
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default:
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hw->dma_int_ena.in_suc_eof = 0;
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hw->dma_int_ena.out_total_eof = 0;
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hw->slave.trans_inten = 1;
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}
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}
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/*------------------------------------------------------------------------------
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* Configs: mode
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*----------------------------------------------------------------------------*/
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/**
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* Enable/disable the postive-cs feature.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param cs One of the CS (0-2) to enable/disable the feature.
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* @param pos_cs true to enable the feature, otherwise disable (default).
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*/
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static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_cs)
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{
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if (pos_cs) {
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hw->misc.master_cs_pol |= (1 << cs);
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} else {
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hw->misc.master_cs_pol &= (1 << cs);
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}
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}
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/**
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* Enable/disable the LSBFIRST feature for TX data.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param lsbfirst true if LSB of TX data to be sent first, otherwise MSB is sent first (default).
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*/
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static inline void spi_ll_set_tx_lsbfirst(spi_dev_t *hw, bool lsbfirst)
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{
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hw->ctrl.wr_bit_order = lsbfirst;
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}
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/**
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* Enable/disable the LSBFIRST feature for RX data.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param lsbfirst true if first bit received as LSB, otherwise as MSB (default).
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*/
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static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst)
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{
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hw->ctrl.rd_bit_order = lsbfirst;
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}
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/**
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* Set SPI mode for the peripheral as master.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param mode SPI mode to work at, 0-3.
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*/
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static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode)
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{
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//Configure polarity
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if (mode == 0) {
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hw->misc.ck_idle_edge = 0;
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hw->user.ck_out_edge = 0;
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} else if (mode == 1) {
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hw->misc.ck_idle_edge = 0;
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hw->user.ck_out_edge = 1;
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} else if (mode == 2) {
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hw->misc.ck_idle_edge = 1;
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hw->user.ck_out_edge = 1;
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} else if (mode == 3) {
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hw->misc.ck_idle_edge = 1;
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hw->user.ck_out_edge = 0;
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}
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}
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/**
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* Set SPI mode for the peripheral as slave.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param mode SPI mode to work at, 0-3.
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*/
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static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma_used)
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{
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if (mode == 0) {
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hw->misc.ck_idle_edge = 0;
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hw->user.rsck_i_edge = 0;
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hw->user.tsck_i_edge = 0;
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hw->ctrl1.rsck_data_out = 0;
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hw->ctrl1.clk_mode_13 = 0;
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} else if (mode == 1) {
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hw->misc.ck_idle_edge = 0;
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hw->user.rsck_i_edge = 1;
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hw->user.tsck_i_edge = 1;
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hw->ctrl1.rsck_data_out = 0;
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hw->ctrl1.clk_mode_13 = 1;
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} else if (mode == 2) {
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hw->misc.ck_idle_edge = 1;
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hw->user.rsck_i_edge = 1;
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hw->user.tsck_i_edge = 1;
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hw->ctrl1.rsck_data_out = 0;
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hw->ctrl1.clk_mode_13 = 0;
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} else if (mode == 3) {
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hw->misc.ck_idle_edge = 1;
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hw->user.rsck_i_edge = 0;
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hw->user.tsck_i_edge = 0;
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hw->ctrl1.rsck_data_out = 0;
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hw->ctrl1.clk_mode_13 = 1;
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}
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//hw->ctrl1.rsck_data_out = 1;
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}
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/**
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* Set SPI to work in full duplex or half duplex mode.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param half_duplex true to work in half duplex mode, otherwise in full duplex mode.
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*/
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static inline void spi_ll_set_half_duplex(spi_dev_t *hw, bool half_duplex)
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{
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hw->user.doutdin = !half_duplex;
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}
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/**
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* Set SPI to work in SIO mode or not.
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*
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* SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param sio_mode true to work in SIO mode, otherwise false.
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*/
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static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode)
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{
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hw->user.sio = sio_mode;
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}
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/**
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* Configure the io mode for the master to work at.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param io_mode IO mode to work at, see ``spi_ll_io_mode_t``.
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*/
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static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_mode)
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{
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hw->ctrl.val &= ~(SPI_FREAD_DUAL | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_QIO);
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hw->user.val &= ~(SPI_FWRITE_DUAL | SPI_FWRITE_QUAD | SPI_FWRITE_DIO | SPI_FWRITE_QIO);
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switch (io_mode) {
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case SPI_LL_IO_MODE_DIO:
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// hw->ctrl.fread_dio = 1;
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// hw->user.fwrite_dio = 1;
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break;
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case SPI_LL_IO_MODE_DUAL:
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hw->ctrl.fread_dual = 1;
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hw->user.fwrite_dual = 1;
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break;
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case SPI_LL_IO_MODE_QIO:
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// hw->ctrl.fread_qio = 1;
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// hw->user.fwrite_qio = 1;
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break;
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case SPI_LL_IO_MODE_QUAD:
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hw->ctrl.fread_quad = 1;
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hw->user.fwrite_quad = 1;
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break;
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default:
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break;
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};
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// if (io_mode != SPI_LL_IO_MODE_NORMAL) {
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// hw->ctrl.fastrd_mode = 1;
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// }
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}
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/**
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* Select one of the CS to use in current transaction.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param cs_id The cs to use, 0-2, otherwise none of them is used.
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*/
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static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id)
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{
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hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1;
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hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1;
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hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1;
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}
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/*------------------------------------------------------------------------------
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* Configs: parameters
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*----------------------------------------------------------------------------*/
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/**
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* Set the clock for master by stored value.
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*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param val stored clock configuration calculated before (by ``spi_ll_cal_clock``).
|
|
*/
|
|
static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, spi_ll_clock_val_t *val)
|
|
{
|
|
hw->clock.val = *(uint32_t *)val;
|
|
}
|
|
|
|
/**
|
|
* Get the frequency of given dividers. Don't use in app.
|
|
*
|
|
* @param fapb APB clock of the system.
|
|
* @param pre Pre devider.
|
|
* @param n main divider.
|
|
*
|
|
* @return Frequency of given dividers.
|
|
*/
|
|
static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n)
|
|
{
|
|
return (fapb / (pre * n));
|
|
}
|
|
|
|
/**
|
|
* Calculate the nearest frequency avaliable for master.
|
|
*
|
|
* @param fapb APB clock of the system.
|
|
* @param hz Frequncy desired.
|
|
* @param duty_cycle Duty cycle desired.
|
|
* @param out_reg Output address to store the calculated clock configurations for the return frequency.
|
|
*
|
|
* @return Actual (nearest) frequency.
|
|
*/
|
|
static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ll_clock_val_t *out_reg)
|
|
{
|
|
typeof(GPSPI2.clock) reg;
|
|
int eff_clk;
|
|
|
|
//In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value.
|
|
if (hz > ((fapb / 4) * 3)) {
|
|
//Using Fapb directly will give us the best result here.
|
|
reg.clkcnt_l = 0;
|
|
reg.clkcnt_h = 0;
|
|
reg.clkcnt_n = 0;
|
|
reg.clkdiv_pre = 0;
|
|
reg.clk_equ_sysclk = 1;
|
|
eff_clk = fapb;
|
|
} else {
|
|
//For best duty cycle resolution, we want n to be as close to 32 as possible, but
|
|
//we also need a pre/n combo that gets us as close as possible to the intended freq.
|
|
//To do this, we bruteforce n and calculate the best pre to go along with that.
|
|
//If there's a choice between pre/n combos that give the same result, use the one
|
|
//with the higher n.
|
|
int pre, n, h, l;
|
|
int bestn = -1;
|
|
int bestpre = -1;
|
|
int besterr = 0;
|
|
int errval;
|
|
for (n = 2; n <= 64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse.
|
|
//Effectively, this does pre=round((fapb/n)/hz).
|
|
pre = ((fapb / n) + (hz / 2)) / hz;
|
|
if (pre <= 0) {
|
|
pre = 1;
|
|
}
|
|
if (pre > 8192) {
|
|
pre = 8192;
|
|
}
|
|
errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz);
|
|
if (bestn == -1 || errval <= besterr) {
|
|
besterr = errval;
|
|
bestn = n;
|
|
bestpre = pre;
|
|
}
|
|
}
|
|
|
|
n = bestn;
|
|
pre = bestpre;
|
|
l = n;
|
|
//This effectively does round((duty_cycle*n)/256)
|
|
h = (duty_cycle * n + 127) / 256;
|
|
if (h <= 0) {
|
|
h = 1;
|
|
}
|
|
|
|
reg.clk_equ_sysclk = 0;
|
|
reg.clkcnt_n = n - 1;
|
|
reg.clkdiv_pre = pre - 1;
|
|
reg.clkcnt_h = h - 1;
|
|
reg.clkcnt_l = l - 1;
|
|
eff_clk = spi_ll_freq_for_pre_n(fapb, pre, n);
|
|
}
|
|
if (out_reg != NULL) {
|
|
*(uint32_t *)out_reg = reg.val;
|
|
}
|
|
return eff_clk;
|
|
}
|
|
|
|
/**
|
|
* Calculate and set clock for SPI master according to desired parameters.
|
|
*
|
|
* This takes long, suggest to calculate the configuration during
|
|
* initialization by ``spi_ll_master_cal_clock`` and store the result, then
|
|
* configure the clock by stored value when used by
|
|
* ``spi_ll_msater_set_clock_by_reg``.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param fapb APB clock of the system.
|
|
* @param hz Frequncy desired.
|
|
* @param duty_cycle Duty cycle desired.
|
|
*
|
|
* @return Actual frequency that is used.
|
|
*/
|
|
static inline int spi_ll_master_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle)
|
|
{
|
|
spi_ll_clock_val_t reg_val;
|
|
int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val);
|
|
spi_ll_master_set_clock_by_reg(hw, ®_val);
|
|
return freq;
|
|
}
|
|
|
|
/**
|
|
* Set the mosi delay after the output edge to the signal. (Preview)
|
|
*
|
|
* The delay mode/num is a Espressif conception, may change in the new chips.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param delay_mode Delay mode, see TRM.
|
|
* @param delay_num APB clocks to delay.
|
|
*/
|
|
static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int delay_num)
|
|
{
|
|
//TODO: this doesn't make sense
|
|
hw->dout_num.dout0_num = 0;
|
|
hw->dout_num.dout1_num = 0;
|
|
}
|
|
|
|
/**
|
|
* Set the miso delay applied to the input signal before the internal peripheral. (Preview)
|
|
*
|
|
* The delay mode/num is a Espressif conception, may change in the new chips.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param delay_mode Delay mode, see TRM.
|
|
* @param delay_num APB clocks to delay.
|
|
*/
|
|
static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int delay_num)
|
|
{
|
|
//TODO: this doesn't make sense
|
|
hw->din_num.din0_num = 1;
|
|
hw->din_num.din1_num = 1;
|
|
}
|
|
|
|
/**
|
|
* Set dummy clocks to output before RX phase (master), or clocks to skip
|
|
* before the data phase and after the address phase (slave).
|
|
*
|
|
* Note this phase is also used to compensate RX timing in half duplex mode.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param dummy_n Dummy cycles used. 0 to disable the dummy phase.
|
|
*/
|
|
static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
|
|
{
|
|
hw->user.usr_dummy = dummy_n ? 1 : 0;
|
|
hw->user1.usr_dummy_cyclelen = dummy_n - 1;
|
|
}
|
|
|
|
/**
|
|
* Set the delay of SPI clocks before the CS inactive edge after the last SPI clock.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param hold Delay of SPI clocks after the last clock, 0 to disable the hold phase.
|
|
*/
|
|
static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold)
|
|
{
|
|
hw->ctrl2.cs_hold_time = hold - 1;
|
|
hw->user.cs_hold = hold ? 1 : 0;
|
|
}
|
|
|
|
/**
|
|
* Set the delay of SPI clocks before the first SPI clock after the CS active edge.
|
|
*
|
|
* Note ESP32 doesn't support to use this feature when command/address phases
|
|
* are used in full duplex mode.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param setup Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
|
|
*/
|
|
static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup)
|
|
{
|
|
hw->ctrl2.cs_setup_time = setup - 1;
|
|
hw->user.cs_setup = setup ? 1 : 0;
|
|
}
|
|
|
|
/**
|
|
* Enable/disable the segment transfer feature for the slave.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param en true to enable, false to disable.
|
|
*/
|
|
static inline void spi_ll_slave_set_seg_en(spi_dev_t *hw, bool en)
|
|
{
|
|
hw->dma_conf.dma_seg_trans_en = en;
|
|
}
|
|
|
|
/*------------------------------------------------------------------------------
|
|
* Configs: data
|
|
*----------------------------------------------------------------------------*/
|
|
/**
|
|
* Set the input length (master).
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param bitlen input length, in bits.
|
|
*/
|
|
static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen)
|
|
{
|
|
hw->miso_dlen.usr_miso_bit_len = bitlen - 1;
|
|
}
|
|
|
|
/**
|
|
* Set the output length (master).
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param bitlen output length, in bits.
|
|
*/
|
|
static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen)
|
|
{
|
|
hw->mosi_dlen.usr_mosi_bit_len = bitlen - 1;
|
|
}
|
|
|
|
/**
|
|
* Set the maximum input length (slave).
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param bitlen input length, in bits.
|
|
*/
|
|
static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen)
|
|
{
|
|
hw->slv_wrbuf_dlen.bit_len = bitlen - 1;
|
|
}
|
|
|
|
/**
|
|
* Set the maximum output length (slave).
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param bitlen output length, in bits.
|
|
*/
|
|
static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen)
|
|
{
|
|
hw->slv_rdbuf_dlen.bit_len = bitlen - 1;
|
|
}
|
|
|
|
/**
|
|
* Set the length of command phase.
|
|
*
|
|
* When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit
|
|
* command phases takes 4 cycles in 4-bit mode.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param bitlen Length of command phase, in bits. 0 to disable the command phase.
|
|
*/
|
|
static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen)
|
|
{
|
|
hw->user2.usr_command_bitlen = bitlen - 1;
|
|
hw->user.usr_command = bitlen ? 1 : 0;
|
|
}
|
|
|
|
/**
|
|
* Set the length of address phase.
|
|
*
|
|
* When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit
|
|
* address phases takes 4 cycles in 4-bit mode.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param bitlen Length of address phase, in bits. 0 to disable the address phase.
|
|
*/
|
|
static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen)
|
|
{
|
|
hw->user1.usr_addr_bitlen = bitlen - 1;
|
|
hw->user.usr_addr = bitlen ? 1 : 0;
|
|
}
|
|
|
|
/**
|
|
* Set the address value in an intuitive way.
|
|
*
|
|
* The length and lsbfirst is required to shift and swap the address to the right place.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param address Address to set
|
|
* @param addrlen Length of the address phase
|
|
* @param lsbfirst whether the LSB first feature is enabled.
|
|
*/
|
|
static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, uint32_t lsbfirst)
|
|
{
|
|
if (lsbfirst) {
|
|
/* The output address start from the LSB of the highest byte, i.e.
|
|
* addr[24] -> addr[31]
|
|
* ...
|
|
* addr[0] -> addr[7]
|
|
* So swap the byte order to let the LSB sent first.
|
|
*/
|
|
addr = HAL_SWAP64(addr);
|
|
if (addrlen > 32) {
|
|
//The slv_wr_status register bits are sent first, then
|
|
//bits in addr register is sent.
|
|
hw->slv_wr_status = addr >> 32;
|
|
hw->addr = addr;
|
|
} else {
|
|
//otherwise only addr register is sent
|
|
hw->addr = addr >> 32;
|
|
}
|
|
} else {
|
|
// shift the address to MSB of addr (and maybe slv_wr_status) register.
|
|
if (addrlen > 32) {
|
|
// output address will be sent from MSB to LSB of slv_wr_status register, then comes the MSB to
|
|
// LSB of addr register.
|
|
hw->addr = addr << (64 - addrlen);
|
|
hw->slv_wr_status = addr >> (addrlen - 32);
|
|
} else {
|
|
// output address will be sent from MSB to LSB of addr register
|
|
hw->addr = addr << (32 - addrlen);
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Set the command value in an intuitive way.
|
|
*
|
|
* The length and lsbfirst is required to shift and swap the command to the right place.
|
|
*
|
|
* @param hw Beginning command of the peripheral registers.
|
|
* @param command Command to set
|
|
* @param addrlen Length of the command phase
|
|
* @param lsbfirst whether the LSB first feature is enabled.
|
|
*/
|
|
static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst)
|
|
{
|
|
if (lsbfirst) {
|
|
// The output command start from bit0 to bit 15, kept as is.
|
|
hw->user2.usr_command_value = cmd;
|
|
} else {
|
|
/* Output command will be sent from bit 7 to 0 of command_value, and
|
|
* then bit 15 to 8 of the same register field. Shift and swap to send
|
|
* more straightly.
|
|
*/
|
|
hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen);
|
|
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Enable/disable the RX data phase.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param enable true if RX phase exist, otherwise false.
|
|
*/
|
|
static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable)
|
|
{
|
|
hw->user.usr_miso = enable;
|
|
}
|
|
|
|
/**
|
|
* Enable/disable the TX data phase.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
* @param enable true if TX phase exist, otherwise false.
|
|
*/
|
|
static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable)
|
|
{
|
|
hw->user.usr_mosi = enable;
|
|
}
|
|
|
|
/**
|
|
* Reset the slave peripheral before next transaction.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
*/
|
|
static inline void spi_ll_slave_reset(spi_dev_t *hw)
|
|
{
|
|
hw->slave.sync_reset = 1;
|
|
hw->slave.sync_reset = 0;
|
|
}
|
|
|
|
/**
|
|
* Get the received bit length of the slave.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers.
|
|
*
|
|
* @return Received bits of the slave.
|
|
*/
|
|
static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
|
|
{
|
|
return hw->slv_rd_byte.slv_rdata_bit * 8;
|
|
}
|
|
|
|
|
|
#undef SPI_LL_RST_MASK
|
|
#undef SPI_LL_UNUSED_INT_MASK
|