107 lines
4.1 KiB
C
107 lines
4.1 KiB
C
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "hal/rmt_hal.h"
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#include "hal/rmt_ll.h"
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void rmt_hal_init(rmt_hal_context_t *hal)
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{
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hal->regs = &RMT;
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hal->mem = &RMTMEM;
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}
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void rmt_hal_reset(rmt_hal_context_t *hal)
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{
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}
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void rmt_hal_channel_reset(rmt_hal_context_t *hal, uint32_t channel)
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{
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rmt_ll_reset_tx_pointer(hal->regs, channel);
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rmt_ll_reset_rx_pointer(hal->regs, channel);
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rmt_ll_enable_err_interrupt(hal->regs, channel, false);
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rmt_ll_enable_tx_end_interrupt(hal->regs, channel, false);
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rmt_ll_enable_tx_thres_interrupt(hal->regs, channel, false);
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rmt_ll_enable_rx_end_interrupt(hal->regs, channel, false);
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rmt_ll_clear_err_interrupt(hal->regs, channel);
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rmt_ll_clear_tx_end_interrupt(hal->regs, channel);
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rmt_ll_clear_tx_thres_interrupt(hal->regs, channel);
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rmt_ll_clear_rx_end_interrupt(hal->regs, channel);
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}
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void rmt_hal_set_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t counter_clk_hz)
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{
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rmt_ll_reset_counter_clock_div(hal->regs, channel);
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uint32_t counter_div = (base_clk_hz + counter_clk_hz / 2) / counter_clk_hz;
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rmt_ll_set_counter_clock_div(hal->regs, channel, counter_div);
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}
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uint32_t rmt_hal_get_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz)
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{
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return base_clk_hz / rmt_ll_get_counter_clock_div(hal->regs, channel);
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}
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void rmt_hal_set_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t carrier_clk_hz, float carrier_clk_duty)
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{
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uint32_t carrier_div = (base_clk_hz + carrier_clk_hz / 2) / carrier_clk_hz;
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uint32_t div_high = (uint32_t)(carrier_div * carrier_clk_duty);
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uint32_t div_low = carrier_div - div_high;
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rmt_ll_set_tx_carrier_high_low_ticks(hal->regs, channel, div_high, div_low);
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}
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void rmt_hal_get_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t *carrier_clk_hz, float *carrier_clk_duty)
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{
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uint32_t div_high = 0;
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uint32_t div_low = 0;
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rmt_ll_get_carrier_high_low_ticks(hal->regs, channel, &div_high, &div_low);
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*carrier_clk_hz = base_clk_hz / (div_high + div_low);
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*carrier_clk_duty = (float)div_high / (div_high + div_low);
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}
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void rmt_hal_set_rx_filter_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us)
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{
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uint32_t thres = (uint32_t)(base_clk_hz / 1e6 * thres_us);
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rmt_ll_set_rx_filter_thres(hal->regs, channel, thres);
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}
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void rmt_hal_set_rx_idle_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us)
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{
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uint32_t thres = (uint32_t)(base_clk_hz / 1e6 * thres_us);
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rmt_ll_set_rx_idle_thres(hal->regs, channel, thres);
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}
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uint32_t rmt_hal_receive(rmt_hal_context_t *hal, uint32_t channel, rmt_item32_t *buf)
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{
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uint32_t len = 0;
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rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_SW);
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for (len = 0; len < SOC_RMT_CHANNEL_MEM_WORDS; len++) {
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buf[len].val = hal->mem->chan[channel].data32[len].val;
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if (!(buf[len].val & 0x7FFF)) {
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break;
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} else if (!(buf[len].val & 0x7FFF0000)) {
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len++;
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break;
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}
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}
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rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_HW);
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rmt_ll_reset_rx_pointer(hal->regs, channel);
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return len;
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}
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void rmt_hal_transmit(rmt_hal_context_t *hal, uint32_t channel, const rmt_item32_t *src, uint32_t length, uint32_t offset)
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{
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rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_SW);
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rmt_ll_write_memory(hal->mem, channel, src, length, offset);
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rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_HW);
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}
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