1. Fix WiFi scan leads to poor performance of Bluetooth. 2. Improve WiFi connect success ratio when coexist with Bluetooth. 3. Check if WiFi is still connected when CSA or beacon timeout happen. 4. add coex pre init
557 lines
18 KiB
C
557 lines
18 KiB
C
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <string.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp32/rom/ets_sys.h"
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#include "esp32/rom/uart.h"
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#include "esp32/rom/rtc.h"
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#include "esp32/rom/cache.h"
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#include "soc/cpu.h"
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#include "soc/rtc.h"
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#include "soc/dport_reg.h"
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#include "soc/gpio_periph.h"
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#include "soc/timer_periph.h"
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#include "soc/rtc_wdt.h"
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#include "soc/efuse_periph.h"
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#include "driver/rtc_io.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/portmacro.h"
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#include "esp_heap_caps_init.h"
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#include "sdkconfig.h"
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#include "esp_system.h"
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#include "esp_spi_flash.h"
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#include "esp_flash_internal.h"
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#include "nvs_flash.h"
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#include "esp_event.h"
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#include "esp_spi_flash.h"
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#include "esp_ipc.h"
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#include "esp_private/crosscore_int.h"
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#include "esp_log.h"
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#include "esp_vfs_dev.h"
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#include "esp_newlib.h"
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#include "esp32/brownout.h"
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#include "esp_int_wdt.h"
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#include "esp_task.h"
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#include "esp_task_wdt.h"
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#include "esp_phy_init.h"
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#include "esp32/cache_err_int.h"
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#include "esp_coexist_internal.h"
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#include "esp_core_dump.h"
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#include "esp_app_trace.h"
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#include "esp_private/dbg_stubs.h"
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#include "esp_flash_encrypt.h"
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#include "esp32/spiram.h"
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#include "esp_clk_internal.h"
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#include "esp_timer.h"
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#include "esp_pm.h"
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#include "esp_private/pm_impl.h"
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#include "trax.h"
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#include "esp_ota_ops.h"
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#include "esp_efuse.h"
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#include "bootloader_flash_config.h"
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#define STRINGIFY(s) STRINGIFY2(s)
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#define STRINGIFY2(s) #s
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void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default"))) __attribute__((noreturn));
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void start_cpu0_default(void) IRAM_ATTR __attribute__((noreturn));
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#if !CONFIG_FREERTOS_UNICORE
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static void IRAM_ATTR call_start_cpu1() __attribute__((noreturn));
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void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default"))) __attribute__((noreturn));
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void start_cpu1_default(void) IRAM_ATTR __attribute__((noreturn));
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static bool app_cpu_started = false;
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#endif //!CONFIG_FREERTOS_UNICORE
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static void do_global_ctors(void);
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static void main_task(void* args);
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extern void app_main(void);
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extern esp_err_t esp_pthread_init(void);
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extern int _bss_start;
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extern int _bss_end;
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extern int _rtc_bss_start;
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extern int _rtc_bss_end;
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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extern int _ext_ram_bss_start;
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extern int _ext_ram_bss_end;
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#endif
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extern int _init_start;
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extern void (*__init_array_start)(void);
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extern void (*__init_array_end)(void);
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extern volatile int port_xSchedulerRunning[2];
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static const char* TAG = "cpu_start";
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struct object { long placeholder[ 10 ]; };
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void __register_frame_info (const void *begin, struct object *ob);
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extern char __eh_frame[];
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//If CONFIG_SPIRAM_IGNORE_NOTFOUND is set and external RAM is not found or errors out on testing, this is set to false.
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static bool s_spiram_okay=true;
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/*
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* We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
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* and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
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*/
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void IRAM_ATTR call_start_cpu0()
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{
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#if CONFIG_FREERTOS_UNICORE
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RESET_REASON rst_reas[1];
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#else
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RESET_REASON rst_reas[2];
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#endif
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cpu_configure_region_protection();
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cpu_init_memctl();
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//Move exception vectors to IRAM
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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rst_reas[0] = rtc_get_reset_reason(0);
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#if !CONFIG_FREERTOS_UNICORE
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rst_reas[1] = rtc_get_reset_reason(1);
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#endif
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// from panic handler we can be reset by RWDT or TG0WDT
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if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET
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#if !CONFIG_FREERTOS_UNICORE
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|| rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
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#endif
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) {
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#ifndef CONFIG_BOOTLOADER_WDT_ENABLE
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rtc_wdt_disable();
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#endif
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}
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//Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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/* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
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if (rst_reas[0] != DEEPSLEEP_RESET) {
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memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
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}
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#if CONFIG_SPIRAM_BOOT_INIT
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esp_spiram_init_cache();
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if (esp_spiram_init() != ESP_OK) {
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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ESP_EARLY_LOGE(TAG, "Failed to init external RAM, needed for external .bss segment");
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abort();
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#endif
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#if CONFIG_SPIRAM_IGNORE_NOTFOUND
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ESP_EARLY_LOGI(TAG, "Failed to init external RAM; continuing without it.");
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s_spiram_okay = false;
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#else
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ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
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abort();
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#endif
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}
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#endif
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ESP_EARLY_LOGI(TAG, "Pro cpu up.");
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if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) {
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const esp_app_desc_t *app_desc = esp_ota_get_app_description();
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ESP_EARLY_LOGI(TAG, "Application information:");
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#ifndef CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR
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ESP_EARLY_LOGI(TAG, "Project name: %s", app_desc->project_name);
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#endif
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#ifndef CONFIG_APP_EXCLUDE_PROJECT_VER_VAR
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ESP_EARLY_LOGI(TAG, "App version: %s", app_desc->version);
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#endif
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#ifdef CONFIG_BOOTLOADER_APP_SECURE_VERSION
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ESP_EARLY_LOGI(TAG, "Secure version: %d", app_desc->secure_version);
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#endif
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#ifdef CONFIG_APP_COMPILE_TIME_DATE
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ESP_EARLY_LOGI(TAG, "Compile time: %s %s", app_desc->date, app_desc->time);
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#endif
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char buf[17];
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esp_ota_get_app_elf_sha256(buf, sizeof(buf));
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ESP_EARLY_LOGI(TAG, "ELF file SHA256: %s...", buf);
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ESP_EARLY_LOGI(TAG, "ESP-IDF: %s", app_desc->idf_ver);
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}
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#if !CONFIG_FREERTOS_UNICORE
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if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU)) {
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ESP_EARLY_LOGE(TAG, "Running on single core chip, but application is built with dual core support.");
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ESP_EARLY_LOGE(TAG, "Please enable CONFIG_FREERTOS_UNICORE option in menuconfig.");
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abort();
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}
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ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
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#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
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esp_flash_encryption_init_checks();
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#endif
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//Flush and enable icache for APP CPU
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Cache_Flush(1);
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Cache_Read_Enable(1);
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esp_cpu_unstall(1);
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// Enable clock and reset APP CPU. Note that OpenOCD may have already
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// enabled clock and taken APP CPU out of reset. In this case don't reset
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// APP CPU again, as that will clear the breakpoints which may have already
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// been set.
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if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
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DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
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DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
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}
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ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
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while (!app_cpu_started) {
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ets_delay_us(100);
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}
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#else
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ESP_EARLY_LOGI(TAG, "Single core mode");
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
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#endif
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#if CONFIG_SPIRAM_MEMTEST
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if (s_spiram_okay) {
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bool ext_ram_ok=esp_spiram_test();
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if (!ext_ram_ok) {
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ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
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abort();
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}
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}
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#endif
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
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#endif
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/* Initialize heap allocator. WARNING: This *needs* to happen *after* the app cpu has booted.
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If the heap allocator is initialized first, it will put free memory linked list items into
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memory also used by the ROM. Starting the app cpu will let its ROM initialize that memory,
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corrupting those linked lists. Initializing the allocator *after* the app cpu has booted
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works around this problem.
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With SPI RAM enabled, there's a second reason: half of the SPI RAM will be managed by the
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app CPU, and when that is not up yet, the memory will be inaccessible and heap_caps_init may
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fail initializing it properly. */
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heap_caps_init();
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ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
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start_cpu0();
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}
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#if !CONFIG_FREERTOS_UNICORE
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static void wdt_reset_cpu1_info_enable(void)
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{
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DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
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DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
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}
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void IRAM_ATTR call_start_cpu1()
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{
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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ets_set_appcpu_boot_addr(0);
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cpu_configure_region_protection();
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cpu_init_memctl();
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#if CONFIG_ESP_CONSOLE_UART_NONE
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ets_install_putc1(NULL);
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ets_install_putc2(NULL);
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#else // CONFIG_ESP_CONSOLE_UART_NONE
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uartAttach();
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ets_install_uart_printf();
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uart_tx_switch(CONFIG_ESP_CONSOLE_UART_NUM);
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#endif
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wdt_reset_cpu1_info_enable();
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ESP_EARLY_LOGI(TAG, "App cpu up.");
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app_cpu_started = 1;
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start_cpu1();
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}
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#endif //!CONFIG_FREERTOS_UNICORE
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static void intr_matrix_clear(void)
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{
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//Clear all the interrupt matrix register
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for (int i = ETS_WIFI_MAC_INTR_SOURCE; i <= ETS_CACHE_IA_INTR_SOURCE; i++) {
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intr_matrix_set(0, i, ETS_INVALID_INUM);
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#if !CONFIG_FREERTOS_UNICORE
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intr_matrix_set(1, i, ETS_INVALID_INUM);
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#endif
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}
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}
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void start_cpu0_default(void)
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{
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esp_err_t err;
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esp_setup_syscall_table();
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if (s_spiram_okay) {
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#if CONFIG_SPIRAM_BOOT_INIT && (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC)
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esp_err_t r=esp_spiram_add_to_heapalloc();
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if (r != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "External RAM could not be added to heap!");
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abort();
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}
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#if CONFIG_SPIRAM_USE_MALLOC
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heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL);
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#endif
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#endif
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}
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//Enable trace memory and immediately start trace.
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#if CONFIG_ESP32_TRAX
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#if CONFIG_ESP32_TRAX_TWOBANKS
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trax_enable(TRAX_ENA_PRO_APP);
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#else
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trax_enable(TRAX_ENA_PRO);
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#endif
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trax_start_trace(TRAX_DOWNCOUNT_WORDS);
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#endif
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esp_clk_init();
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esp_perip_clk_init();
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intr_matrix_clear();
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#ifndef CONFIG_ESP_CONSOLE_UART_NONE
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#ifdef CONFIG_PM_ENABLE
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const int uart_clk_freq = REF_CLK_FREQ;
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/* When DFS is enabled, use REFTICK as UART clock source */
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CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_ESP_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
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#else
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const int uart_clk_freq = APB_CLK_FREQ;
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#endif // CONFIG_PM_DFS_ENABLE
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uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
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#endif // CONFIG_ESP_CONSOLE_UART_NONE
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#if CONFIG_ESP32_BROWNOUT_DET
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esp_brownout_init();
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#endif
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#if CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE
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esp_efuse_disable_basic_rom_console();
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#endif
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rtc_gpio_force_hold_dis_all();
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esp_vfs_dev_uart_register();
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esp_reent_init(_GLOBAL_REENT);
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#ifndef CONFIG_ESP_CONSOLE_UART_NONE
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const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_ESP_CONSOLE_UART_NUM);
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_GLOBAL_REENT->_stdin = fopen(default_uart_dev, "r");
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_GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
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_GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
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#else
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_GLOBAL_REENT->_stdin = (FILE*) &__sf_fake_stdin;
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_GLOBAL_REENT->_stdout = (FILE*) &__sf_fake_stdout;
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_GLOBAL_REENT->_stderr = (FILE*) &__sf_fake_stderr;
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#endif
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esp_timer_init();
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esp_set_time_from_rtc();
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#if CONFIG_ESP32_APPTRACE_ENABLE
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err = esp_apptrace_init();
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assert(err == ESP_OK && "Failed to init apptrace module on PRO CPU!");
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#endif
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#if CONFIG_SYSVIEW_ENABLE
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SEGGER_SYSVIEW_Conf();
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#endif
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#if CONFIG_ESP32_DEBUG_STUBS_ENABLE
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esp_dbg_stubs_init();
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#endif
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err = esp_pthread_init();
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assert(err == ESP_OK && "Failed to init pthread module!");
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do_global_ctors();
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#if CONFIG_ESP_INT_WDT
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esp_int_wdt_init();
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//Initialize the interrupt watch dog for CPU0.
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esp_int_wdt_cpu_init();
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#endif
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esp_cache_err_int_init();
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esp_crosscore_int_init();
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#ifndef CONFIG_FREERTOS_UNICORE
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esp_dport_access_int_init();
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#endif
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spi_flash_init();
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/* init default OS-aware flash access critical section */
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spi_flash_guard_set(&g_flash_guard_default_ops);
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esp_flash_app_init();
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esp_err_t flash_ret = esp_flash_init_default_chip();
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assert(flash_ret == ESP_OK);
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#ifdef CONFIG_PM_ENABLE
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esp_pm_impl_init();
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#ifdef CONFIG_PM_DFS_INIT_AUTO
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int xtal_freq = (int) rtc_clk_xtal_freq_get();
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esp_pm_config_esp32_t cfg = {
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.max_freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ,
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.min_freq_mhz = xtal_freq,
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};
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esp_pm_configure(&cfg);
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#endif //CONFIG_PM_DFS_INIT_AUTO
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#endif //CONFIG_PM_ENABLE
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#if CONFIG_ESP32_ENABLE_COREDUMP
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esp_core_dump_init();
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size_t core_data_sz = 0;
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size_t core_data_addr = 0;
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if (esp_core_dump_image_get(&core_data_addr, &core_data_sz) == ESP_OK && core_data_sz > 0) {
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ESP_LOGI(TAG, "Found core dump %d bytes in flash @ 0x%x", core_data_sz, core_data_addr);
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}
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#endif
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#if CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
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esp_coex_adapter_register(&g_coex_adapter_funcs);
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coex_pre_init();
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#endif
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bootloader_flash_update_id();
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#if !CONFIG_SPIRAM_BOOT_INIT
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// Read the application binary image header. This will also decrypt the header if the image is encrypted.
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esp_image_header_t fhdr = {0};
|
|
// This assumes that DROM is the first segment in the application binary, i.e. that we can read
|
|
// the binary header through cache by accessing SOC_DROM_LOW address.
|
|
memcpy(&fhdr, (void*) SOC_DROM_LOW, sizeof(fhdr));
|
|
// If psram is uninitialized, we need to improve some flash configuration.
|
|
bootloader_flash_clock_config(&fhdr);
|
|
bootloader_flash_gpio_config(&fhdr);
|
|
bootloader_flash_dummy_config(&fhdr);
|
|
bootloader_flash_cs_timing_config();
|
|
#endif
|
|
|
|
portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
|
|
ESP_TASK_MAIN_STACK, NULL,
|
|
ESP_TASK_MAIN_PRIO, NULL, 0);
|
|
assert(res == pdTRUE);
|
|
ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
|
|
vTaskStartScheduler();
|
|
abort(); /* Only get to here if not enough free heap to start scheduler */
|
|
}
|
|
|
|
#if !CONFIG_FREERTOS_UNICORE
|
|
void start_cpu1_default(void)
|
|
{
|
|
// Wait for FreeRTOS initialization to finish on PRO CPU
|
|
while (port_xSchedulerRunning[0] == 0) {
|
|
;
|
|
}
|
|
#if CONFIG_ESP32_TRAX_TWOBANKS
|
|
trax_start_trace(TRAX_DOWNCOUNT_WORDS);
|
|
#endif
|
|
#if CONFIG_ESP32_APPTRACE_ENABLE
|
|
esp_err_t err = esp_apptrace_init();
|
|
assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
|
|
#endif
|
|
#if CONFIG_ESP_INT_WDT
|
|
//Initialize the interrupt watch dog for CPU1.
|
|
esp_int_wdt_cpu_init();
|
|
#endif
|
|
//Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
|
|
//has started, but it isn't active *on this CPU* yet.
|
|
esp_cache_err_int_init();
|
|
esp_crosscore_int_init();
|
|
esp_dport_access_int_init();
|
|
|
|
ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
|
|
xPortStartScheduler();
|
|
abort(); /* Only get to here if FreeRTOS somehow very broken */
|
|
}
|
|
#endif //!CONFIG_FREERTOS_UNICORE
|
|
|
|
#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
|
|
size_t __cxx_eh_arena_size_get()
|
|
{
|
|
return CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE;
|
|
}
|
|
#endif
|
|
|
|
static void do_global_ctors(void)
|
|
{
|
|
#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
|
|
static struct object ob;
|
|
__register_frame_info( __eh_frame, &ob );
|
|
#endif
|
|
|
|
void (**p)(void);
|
|
for (p = &__init_array_end - 1; p >= &__init_array_start; --p) {
|
|
(*p)();
|
|
}
|
|
}
|
|
|
|
static void main_task(void* args)
|
|
{
|
|
#if !CONFIG_FREERTOS_UNICORE
|
|
// Wait for FreeRTOS initialization to finish on APP CPU, before replacing its startup stack
|
|
while (port_xSchedulerRunning[1] == 0) {
|
|
;
|
|
}
|
|
#endif
|
|
//Enable allocation in region where the startup stacks were located.
|
|
heap_caps_enable_nonos_stack_heaps();
|
|
|
|
// Now we have startup stack RAM available for heap, enable any DMA pool memory
|
|
#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
|
|
esp_err_t r = esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
|
|
if (r != ESP_OK) {
|
|
ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool (error 0x%x)", r);
|
|
abort();
|
|
}
|
|
#endif
|
|
|
|
//Initialize task wdt if configured to do so
|
|
#ifdef CONFIG_ESP_TASK_WDT_PANIC
|
|
ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true));
|
|
#elif CONFIG_ESP_TASK_WDT
|
|
ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false));
|
|
#endif
|
|
|
|
//Add IDLE 0 to task wdt
|
|
#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
|
|
TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
|
|
if(idle_0 != NULL){
|
|
ESP_ERROR_CHECK(esp_task_wdt_add(idle_0));
|
|
}
|
|
#endif
|
|
//Add IDLE 1 to task wdt
|
|
#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
|
|
TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
|
|
if(idle_1 != NULL){
|
|
ESP_ERROR_CHECK(esp_task_wdt_add(idle_1));
|
|
}
|
|
#endif
|
|
|
|
// Now that the application is about to start, disable boot watchdog
|
|
#ifndef CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE
|
|
rtc_wdt_disable();
|
|
#endif
|
|
#ifdef CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
|
|
const esp_partition_t *efuse_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_EFUSE_EM, NULL);
|
|
if (efuse_partition) {
|
|
esp_efuse_init(efuse_partition->address, efuse_partition->size);
|
|
}
|
|
#endif
|
|
app_main();
|
|
vTaskDelete(NULL);
|
|
}
|
|
|