Xia Xiaotian f1daea79f7 soc: clear PHY status when cpu start		2020-02-13 14:30:10 +08:00
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esp32	soc: clear PHY status when cpu start	2020-02-13 14:30:10 +08:00
include/soc	soc: Fix esp_ptr_executable() for single core ESP32 config & cache memory	2020-01-29 10:05:04 +11:00
test	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
CMakeLists.txt	cmake: make main a component again	2018-09-13 11:13:27 +08:00
component.mk	Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.	2017-09-04 12:05:49 +08:00