78 lines
4.7 KiB
C
78 lines
4.7 KiB
C
#pragma once
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/* declare the performance here */
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#define IDF_PERFORMANCE_MAX_HTTPS_REQUEST_BIN_SIZE 900
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP 200
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_PSRAM 300
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE 130
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#define IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL 1000
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_ESP32 30
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA_ESP32 27
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_ESP32S2 32
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA_ESP32S2 30
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
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/* Due to code size & linker layout differences interacting with cache, VFS
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microbenchmark currently runs slower with PSRAM enabled. */
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#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME 20000
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#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM 25000
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// throughput performance by iperf
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#define IDF_PERFORMANCE_MIN_TCP_RX_THROUGHPUT 45
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#define IDF_PERFORMANCE_MIN_TCP_TX_THROUGHPUT 40
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#define IDF_PERFORMANCE_MIN_UDP_RX_THROUGHPUT 64
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#define IDF_PERFORMANCE_MIN_UDP_TX_THROUGHPUT 50
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// events dispatched per second by event loop library
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#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH 25000
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#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM 21000
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// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
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#define IDF_PERFORMANCE_MAX_ESP32_CYCLES_PER_DIV 70
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#define IDF_PERFORMANCE_MAX_ESP32_CYCLES_PER_SQRT 140
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#define IDF_PERFORMANCE_MAX_SPILL_REG_CYCLES 150
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#define IDF_PERFORMANCE_MAX_ISR_ENTER_CYCLES 290
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#define IDF_PERFORMANCE_MAX_ISR_EXIT_CYCLES 565
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_TOHOST_4BIT 12500
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_FRHOST_4BIT 12500
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_TOHOST_1BIT 4000
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_FRHOST_1BIT 4000
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_TOHOST_SPI 1000
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_FRHOST_SPI 1000
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#ifdef CONFIG_IDF_TARGET_ESP32
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// AES-CBC hardware throughput (accounts for worst-case performance with PSRAM workaround)
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#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 8.2
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// SHA256 hardware throughput at 240MHz, threshold set lower than worst case
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#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 9.0
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// esp_sha() time to process 32KB of input data from RAM
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#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 5000
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#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 4500
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#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 19000
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#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 180000
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#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 65000
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#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 850000
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#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
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#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 14.4
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// SHA256 hardware throughput at 240MHz, threshold set lower than worst case
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#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 19.8
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// esp_sha() time to process 32KB of input data from RAM
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#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 1000
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#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900
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#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 14000
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#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 100000
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#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 60000
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#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 600000
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#endif //CONFIG_IDF_TARGET_ESP32S2BETA
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