eb14284c92
1. Add disable PHY and RF when WiFi and BT are both disabled(including call sniffer disable API). 2. Do not init PHY and RF when cpu start. Init PHY and RF when call Wifi or BT start APIs(including sniffer enable API). 3. Add a temporary lib: librtc_clk.a and will delete it when CPU frequency switching function is done. 4. Add an function to get OS tick rate. 5. Do not put the whole pp.a in iram0, only put lmac.o, ieee80211_misc.o, ets_time.o and wdev.o in iram0.
147 lines
4.7 KiB
C
147 lines
4.7 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/**
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* @file rtc.h
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* @brief Declarations of APIs provided by librtc.a
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*
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* This file is not in the include directory of esp32 component, so it is not
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* part of the public API. As the source code of librtc.a is gradually moved
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* into the ESP-IDF, some of these APIs will be exposed to applications.
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*
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* For now, only esp_deep_sleep function declared in esp_deepsleep.h
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* is part of public API.
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*/
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#pragma once
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#include <stdint.h>
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#include <stddef.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum{
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XTAL_40M = 40,
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XTAL_26M = 26,
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XTAL_24M = 24,
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XTAL_AUTO = 0
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} xtal_freq_t;
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typedef enum{
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CPU_XTAL = 0,
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CPU_80M = 1,
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CPU_160M = 2,
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CPU_240M = 3,
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CPU_2M = 4
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} cpu_freq_t;
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typedef enum {
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CALI_RTC_MUX = 0,
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CALI_8MD256 = 1,
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CALI_32K_XTAL = 2
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} cali_clk_t;
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/**
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* This function must be called to initialize RTC library
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* @param xtal_freq Frequency of main crystal
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*/
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void rtc_init_lite(xtal_freq_t xtal_freq);
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/**
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* Switch CPU frequency
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* @param cpu_freq new CPU frequency
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*/
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void rtc_set_cpu_freq(cpu_freq_t cpu_freq);
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/**
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* @brief Return RTC slow clock's period
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* @param cali_clk clock to calibrate
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* @param slow_clk_cycles number of slow clock cycles to average
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* @param xtal_freq chip's main XTAL freq
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* @return average slow clock period in microseconds, Q13.19 fixed point format
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*/
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uint32_t rtc_slowck_cali(cali_clk_t cali_clk, uint32_t slow_clk_cycles);
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/**
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* @brief Convert from microseconds to slow clock cycles
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* @param time_in_us_h Time in microseconds, higher 32 bit part
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* @param time_in_us_l Time in microseconds, lower 32 bit part
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* @param slow_clk_period Period of slow clock in microseconds, Q13.19 fixed point format (as returned by rtc_slowck_cali).
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* @param[out] cylces_h output, higher 32 bit part of number of slow clock cycles
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* @param[out] cycles_l output, lower 32 bit part of number of slow clock cycles
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*/
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void rtc_usec2rtc(uint32_t time_in_us_h, uint32_t time_in_us_l, uint32_t slow_clk_period, uint32_t *cylces_h, uint32_t *cycles_l);
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#define DEEP_SLEEP_PD_NORMAL BIT(0) /*!< Base deep sleep mode */
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#define DEEP_SLEEP_PD_RTC_PERIPH BIT(1) /*!< Power down RTC peripherals */
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#define DEEP_SLEEP_PD_RTC_SLOW_MEM BIT(2) /*!< Power down RTC SLOW memory */
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#define DEEP_SLEEP_PD_RTC_FAST_MEM BIT(3) /*!< Power down RTC FAST memory */
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/**
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* @brief Prepare for entering sleep mode
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* @param deep_slp DEEP_SLEEP_PD_ flags combined with OR (DEEP_SLEEP_PD_NORMAL must be included)
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* @param cpu_lp_mode for deep sleep, should be 0
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*/
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void rtc_slp_prep_lite(uint32_t deep_slp, uint32_t cpu_lp_mode);
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#define RTC_EXT_EVENT0_TRIG BIT(0)
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#define RTC_EXT_EVENT1_TRIG BIT(1)
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#define RTC_GPIO_TRIG BIT(2)
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#define RTC_TIMER_EXPIRE BIT(3)
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#define RTC_SDIO_TRIG BIT(4)
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#define RTC_MAC_TRIG BIT(5)
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#define RTC_UART0_TRIG BIT(6)
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#define RTC_UART1_TRIG BIT(7)
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#define RTC_TOUCH_TRIG BIT(8)
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#define RTC_SAR_TRIG BIT(9)
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#define RTC_BT_TRIG BIT(10)
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#define RTC_EXT_EVENT0_TRIG_EN RTC_EXT_EVENT0_TRIG
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#define RTC_EXT_EVENT1_TRIG_EN RTC_EXT_EVENT1_TRIG
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#define RTC_GPIO_TRIG_EN RTC_GPIO_TRIG
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#define RTC_TIMER_EXPIRE_EN RTC_TIMER_EXPIRE
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#define RTC_SDIO_TRIG_EN RTC_SDIO_TRIG
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#define RTC_MAC_TRIG_EN RTC_MAC_TRIG
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#define RTC_UART0_TRIG_EN RTC_UART0_TRIG
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#define RTC_UART1_TRIG_EN RTC_UART1_TRIG
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#define RTC_TOUCH_TRIG_EN RTC_TOUCH_TRIG
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#define RTC_SAR_TRIG_EN RTC_SAR_TRIG
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#define RTC_BT_TRIG_EN RTC_BT_TRIG
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/**
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* @brief Enter sleep mode for given number of cycles
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* @param cycles_h higher 32 bit part of number of slow clock cycles
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* @param cycles_l lower 32 bit part of number of slow clock cycles
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* @param wakeup_opt wake up reason to enable (RTC_xxx_EN flags combined with OR)
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* @param reject_opt reserved, should be 0
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* @return TBD
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*/
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uint32_t rtc_sleep(uint32_t cycles_h, uint32_t cycles_l, uint32_t wakeup_opt, uint32_t reject_opt);
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/**
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* @brief Shutdown PHY and RF. This is a temporary function.
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*/
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void pm_close_rf(void);
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#ifdef __cplusplus
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}
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#endif
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