357 lines
10 KiB
C
357 lines
10 KiB
C
/*
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* ESP32 hardware accelerated SHA1/256/512 implementation
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* based on mbedTLS FIPS-197 compliant version.
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*
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* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
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* Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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/*
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* The SHA-1 standard was published by NIST in 1993.
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*
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* http://www.itl.nist.gov/fipspubs/fip180-1.htm
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*/
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#include <string.h>
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#include <stdio.h>
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#include <byteswap.h>
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#include <assert.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "hwcrypto/sha.h"
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#include "rom/ets_sys.h"
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#include "soc/dport_reg.h"
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#include "soc/hwcrypto_reg.h"
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#include "driver/periph_ctrl.h"
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inline static uint32_t SHA_LOAD_REG(esp_sha_type sha_type) {
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return SHA_1_LOAD_REG + sha_type * 0x10;
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}
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inline static uint32_t SHA_BUSY_REG(esp_sha_type sha_type) {
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return SHA_1_BUSY_REG + sha_type * 0x10;
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}
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inline static uint32_t SHA_START_REG(esp_sha_type sha_type) {
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return SHA_1_START_REG + sha_type * 0x10;
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}
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inline static uint32_t SHA_CONTINUE_REG(esp_sha_type sha_type) {
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return SHA_1_CONTINUE_REG + sha_type * 0x10;
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}
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/* Single spinlock for SHA engine memory block
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*/
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static portMUX_TYPE memory_block_lock = portMUX_INITIALIZER_UNLOCKED;
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/* Binary semaphore managing the state of each concurrent SHA engine.
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Available = noone is using this SHA engine
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Taken = a SHA session is running on this SHA engine
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Indexes:
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0 = SHA1
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1 = SHA2_256
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2 = SHA2_384 or SHA2_512
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*/
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static SemaphoreHandle_t engine_states[3];
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static uint8_t engines_in_use;
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/* Spinlock for engines_in_use counter
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*/
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static portMUX_TYPE engines_in_use_lock = portMUX_INITIALIZER_UNLOCKED;
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/* Index into the engine_states array */
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inline static size_t sha_engine_index(esp_sha_type type) {
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switch(type) {
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case SHA1:
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return 0;
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case SHA2_256:
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return 1;
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default:
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return 2;
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}
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}
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/* Return digest length (in bytes) for a given SHA type */
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inline static size_t sha_length(esp_sha_type type) {
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switch(type) {
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case SHA1:
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return 20;
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case SHA2_256:
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return 32;
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case SHA2_384:
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return 48;
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case SHA2_512:
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return 64;
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default:
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return 0;
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}
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}
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/* Return block size (in bytes) for a given SHA type */
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inline static size_t block_length(esp_sha_type type) {
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switch(type) {
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case SHA1:
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case SHA2_256:
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return 64;
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case SHA2_384:
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case SHA2_512:
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return 128;
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default:
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return 0;
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}
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}
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void esp_sha_lock_memory_block(void)
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{
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portENTER_CRITICAL(&memory_block_lock);
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}
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void esp_sha_unlock_memory_block(void)
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{
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portEXIT_CRITICAL(&memory_block_lock);
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}
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static SemaphoreHandle_t sha_get_engine_state(esp_sha_type sha_type)
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{
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unsigned idx = sha_engine_index(sha_type);
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volatile SemaphoreHandle_t *engine = &engine_states[idx];
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SemaphoreHandle_t result = *engine;
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if (result == NULL) {
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// Create a new semaphore for 'in use' flag
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SemaphoreHandle_t new_engine = xSemaphoreCreateBinary();
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assert(new_engine != NULL);
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xSemaphoreGive(new_engine); // start available
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// try to atomically set the previously NULL *engine to new_engine
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uint32_t set_engine = (uint32_t)new_engine;
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uxPortCompareSet((volatile uint32_t *)engine, 0, &set_engine);
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if (set_engine != 0) { // we lost a race setting *engine
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vSemaphoreDelete(new_engine);
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}
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result = *engine;
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}
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return result;
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}
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static bool esp_sha_lock_engine_common(esp_sha_type sha_type, TickType_t ticks_to_wait);
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bool esp_sha_try_lock_engine(esp_sha_type sha_type)
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{
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return esp_sha_lock_engine_common(sha_type, 0);
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}
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void esp_sha_lock_engine(esp_sha_type sha_type)
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{
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esp_sha_lock_engine_common(sha_type, portMAX_DELAY);
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}
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static bool esp_sha_lock_engine_common(esp_sha_type sha_type, TickType_t ticks_to_wait)
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{
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SemaphoreHandle_t engine_state = sha_get_engine_state(sha_type);
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BaseType_t result = xSemaphoreTake(engine_state, ticks_to_wait);
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if (result == pdFALSE) {
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// failed to take semaphore
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return false;
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}
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portENTER_CRITICAL(&engines_in_use_lock);
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if (engines_in_use == 0) {
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/* Just locked first engine,
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so enable SHA hardware */
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periph_module_enable(PERIPH_SHA_MODULE);
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}
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engines_in_use++;
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assert(engines_in_use <= 3);
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portEXIT_CRITICAL(&engines_in_use_lock);
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return true;
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}
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void esp_sha_unlock_engine(esp_sha_type sha_type)
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{
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SemaphoreHandle_t *engine_state = sha_get_engine_state(sha_type);
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portENTER_CRITICAL(&engines_in_use_lock);
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engines_in_use--;
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if (engines_in_use == 0) {
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/* About to release last engine, so
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disable SHA hardware */
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periph_module_disable(PERIPH_SHA_MODULE);
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}
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portEXIT_CRITICAL(&engines_in_use_lock);
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xSemaphoreGive(engine_state);
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}
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void esp_sha_wait_idle(void)
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{
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while(1) {
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if(DPORT_REG_READ(SHA_1_BUSY_REG) == 0
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&& DPORT_REG_READ(SHA_256_BUSY_REG) == 0
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&& DPORT_REG_READ(SHA_384_BUSY_REG) == 0
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&& DPORT_REG_READ(SHA_512_BUSY_REG) == 0) {
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break;
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}
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}
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}
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void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state)
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{
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#ifndef NDEBUG
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{
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SemaphoreHandle_t *engine_state = sha_get_engine_state(sha_type);
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assert(uxSemaphoreGetCount(engine_state) == 0 &&
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"SHA engine should be locked" );
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}
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#endif
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// preemptively do this before entering the critical section, then re-check once in it
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esp_sha_wait_idle();
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esp_sha_lock_memory_block();
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esp_sha_wait_idle();
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DPORT_REG_WRITE(SHA_LOAD_REG(sha_type), 1);
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while(DPORT_REG_READ(SHA_BUSY_REG(sha_type)) == 1) { }
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uint32_t *digest_state_words = (uint32_t *)digest_state;
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uint32_t *reg_addr_buf = (uint32_t *)(SHA_TEXT_BASE);
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if(sha_type == SHA2_384 || sha_type == SHA2_512) {
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/* for these ciphers using 64-bit states, swap each pair of words */
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DPORT_INTERRUPT_DISABLE(); // Disable interrupt only on current CPU.
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for(int i = 0; i < sha_length(sha_type)/4; i += 2) {
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digest_state_words[i+1] = DPORT_SEQUENCE_REG_READ((uint32_t)®_addr_buf[i]);
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digest_state_words[i] = DPORT_SEQUENCE_REG_READ((uint32_t)®_addr_buf[i+1]);
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}
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DPORT_INTERRUPT_RESTORE(); // restore the previous interrupt level
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} else {
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esp_dport_access_read_buffer(digest_state_words, (uint32_t)®_addr_buf[0], sha_length(sha_type)/4);
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}
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esp_sha_unlock_memory_block();
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}
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void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block)
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{
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#ifndef NDEBUG
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{
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SemaphoreHandle_t *engine_state = sha_get_engine_state(sha_type);
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assert(uxSemaphoreGetCount(engine_state) == 0 &&
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"SHA engine should be locked" );
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}
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#endif
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// preemptively do this before entering the critical section, then re-check once in it
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esp_sha_wait_idle();
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esp_sha_lock_memory_block();
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esp_sha_wait_idle();
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/* Fill the data block */
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uint32_t *reg_addr_buf = (uint32_t *)(SHA_TEXT_BASE);
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uint32_t *data_words = (uint32_t *)data_block;
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for (int i = 0; i < block_length(sha_type) / 4; i++) {
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reg_addr_buf[i] = __bswap_32(data_words[i]);
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}
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asm volatile ("memw");
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if(is_first_block) {
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DPORT_REG_WRITE(SHA_START_REG(sha_type), 1);
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} else {
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DPORT_REG_WRITE(SHA_CONTINUE_REG(sha_type), 1);
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}
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esp_sha_unlock_memory_block();
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/* Note: deliberately not waiting for this operation to complete,
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as a performance tweak - delay waiting until the next time we need the SHA
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unit, instead.
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*/
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}
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void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output)
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{
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size_t block_len = block_length(sha_type);
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// Max number of blocks to pass per each call to esp_sha_lock_memory_block()
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// (keep low enough to avoid starving interrupt handlers, especially if reading
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// data into SHA via flash cache, but high enough that spinlock overhead is low)
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const size_t BLOCKS_PER_CHUNK = 100;
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const size_t MAX_CHUNK_LEN = BLOCKS_PER_CHUNK * block_len;
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esp_sha_lock_engine(sha_type);
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SHA_CTX ctx;
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ets_sha_init(&ctx);
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while (ilen > 0) {
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size_t chunk_len = (ilen > MAX_CHUNK_LEN) ? MAX_CHUNK_LEN : ilen;
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// Wait for idle before entering critical section
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// (to reduce time spent in it), then check again after
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esp_sha_wait_idle();
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esp_sha_lock_memory_block();
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esp_sha_wait_idle();
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DPORT_STALL_OTHER_CPU_START();
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while (chunk_len > 0) {
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// This SHA ROM function reads DPORT regs
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// (can accept max one SHA block each call)
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size_t update_len = (chunk_len > block_len) ? block_len : chunk_len;
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ets_sha_update(&ctx, sha_type, input, update_len * 8);
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input += update_len;
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chunk_len -= update_len;
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ilen -= update_len;
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}
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DPORT_STALL_OTHER_CPU_END();
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if (ilen == 0) {
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/* Finish the last block before releasing the memory
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block lock, as ets_sha_update() may have written data to
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the memory block already (partial last block) and hardware
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hasn't yet processed it.
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*/
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DPORT_STALL_OTHER_CPU_START();
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{
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// This SHA ROM function also reads DPORT regs
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ets_sha_finish(&ctx, sha_type, output);
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}
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DPORT_STALL_OTHER_CPU_END();
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}
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esp_sha_unlock_memory_block();
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}
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esp_sha_unlock_engine(sha_type);
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}
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