301dacfb33
Configurable option to use IRAM as byte accessible memory (in single core mode) using load-store (non-word aligned and non-word size IRAM access specific) exception handlers. This allows to use IRAM for use-cases where certain performance penalty (upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration option has been provided to redirect mbedTLS specific in-out content length buffers to IRAM (in single core mode), allows to save 20KB per TLS connection. |
||
|---|---|---|
| .. | ||
| esp_heap_caps.h | ||
| esp_heap_caps_init.h | ||
| esp_heap_task_info.h | ||
| esp_heap_trace.h | ||
| heap_trace.inc | ||
| multi_heap.h | ||