e76c187efb
MR !441 (7c155ab) has fixed issue with esp_intr_noniram_{disable,enable}
calls not being properly protected by spi_flash_op_{lock,unlock}.
Unit test was added, but the unit test environment tests only dual-core
config. Similar issue was present in the code path for the single-core
config, where esp_intr_noniram_{disable,enable} calls were unprotected.
This change fixes the protection issue and updates the unit test to
run properly in single core config as well.
The issue with running unit tests for single core config will be
addressed in a separate MR.
92 lines
2.8 KiB
C
92 lines
2.8 KiB
C
#include <stdio.h>
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#include <freertos/FreeRTOS.h>
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#include <freertos/task.h>
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#include <freertos/semphr.h>
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#include <unity.h>
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#include <esp_spi_flash.h>
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#include <esp_attr.h>
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#include "test_config.h"
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struct flash_test_ctx {
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uint32_t offset;
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bool fail;
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SemaphoreHandle_t done;
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};
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static void flash_test_task(void *arg)
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{
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struct flash_test_ctx *ctx = (struct flash_test_ctx *) arg;
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vTaskDelay(100 / portTICK_PERIOD_MS);
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const uint32_t sector = ctx->offset;
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printf("t%d\n", sector);
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printf("es%d\n", sector);
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if (spi_flash_erase_sector(sector) != ESP_OK) {
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ctx->fail = true;
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printf("Erase failed\r\n");
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xSemaphoreGive(ctx->done);
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vTaskDelete(NULL);
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}
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printf("ed%d\n", sector);
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vTaskDelay(0 / portTICK_PERIOD_MS);
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uint32_t val = 0xabcd1234;
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for (uint32_t offset = 0; offset < SPI_FLASH_SEC_SIZE; offset += 4) {
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if (spi_flash_write(sector * SPI_FLASH_SEC_SIZE + offset, (const uint8_t *) &val, 4) != ESP_OK) {
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printf("Write failed at offset=%d\r\n", offset);
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ctx->fail = true;
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break;
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}
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}
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printf("wd%d\n", sector);
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vTaskDelay(0 / portTICK_PERIOD_MS);
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uint32_t val_read;
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for (uint32_t offset = 0; offset < SPI_FLASH_SEC_SIZE; offset += 4) {
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if (spi_flash_read(sector * SPI_FLASH_SEC_SIZE + offset, (uint8_t *) &val_read, 4) != ESP_OK) {
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printf("Read failed at offset=%d\r\n", offset);
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ctx->fail = true;
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break;
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}
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if (val_read != val) {
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printf("Read invalid value=%08x at offset=%d\r\n", val_read, offset);
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ctx->fail = true;
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break;
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}
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}
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printf("td%d\n", sector);
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xSemaphoreGive(ctx->done);
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vTaskDelete(NULL);
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}
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TEST_CASE("flash write and erase work both on PRO CPU and on APP CPU", "[spi_flash][ignore]")
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{
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SemaphoreHandle_t done = xSemaphoreCreateCounting(4, 0);
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struct flash_test_ctx ctx[] = {
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{ .offset = 0x100 + 6, .done = done },
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{ .offset = 0x100 + 7, .done = done },
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{ .offset = 0x100 + 8, .done = done },
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#ifndef CONFIG_FREERTOS_UNICORE
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{ .offset = 0x100 + 9, .done = done }
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#endif
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};
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xTaskCreatePinnedToCore(flash_test_task, "t0", 2048, &ctx[0], 3, NULL, 0);
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xTaskCreatePinnedToCore(flash_test_task, "t1", 2048, &ctx[1], 3, NULL, tskNO_AFFINITY);
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xTaskCreatePinnedToCore(flash_test_task, "t2", 2048, &ctx[2], 3, NULL, tskNO_AFFINITY);
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#ifndef CONFIG_FREERTOS_UNICORE
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xTaskCreatePinnedToCore(flash_test_task, "t3", 2048, &ctx[3], 3, NULL, 1);
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#endif
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const size_t task_count = sizeof(ctx)/sizeof(ctx[0]);
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for (int i = 0; i < task_count; ++i) {
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xSemaphoreTake(done, portMAX_DELAY);
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TEST_ASSERT_FALSE(ctx[i].fail);
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}
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vSemaphoreDelete(done);
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}
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