159 lines
7.6 KiB
ReStructuredText
159 lines
7.6 KiB
ReStructuredText
SPI Master driver
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=================
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Overview
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--------
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The ESP32 has four SPI peripheral devices, called SPI0, SPI1, HSPI and VSPI. SPI0 is entirely dedicated to
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the flash cache the ESP32 uses to map the SPI flash device it is connected to into memory. SPI1 is
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connected to the same hardware lines as SPI0 and is used to write to the flash chip. HSPI and VSPI
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are free to use. SPI1, HSPI and VSPI all have three chip select lines, allowing them to drive up to
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three SPI devices each as a master.
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The spi_master driver
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^^^^^^^^^^^^^^^^^^^^^
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The spi_master driver allows easy communicating with SPI slave devices, even in a multithreaded environment.
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It fully transparently handles DMA transfers to read and write data and automatically takes care of
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multiplexing between different SPI slaves on the same master
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Terminology
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^^^^^^^^^^^
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The spi_master driver uses the following terms:
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* Host: The SPI peripheral inside the ESP32 initiating the SPI transmissions. One of SPI, HSPI or VSPI. (For
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now, only HSPI or VSPI are actually supported in the driver; it will support all 3 peripherals
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somewhere in the future.)
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* Bus: The SPI bus, common to all SPI devices connected to one host. In general the bus consists of the
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miso, mosi, sclk and optionally quadwp and quadhd signals. The SPI slaves are connected to these
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signals in parallel.
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- miso - Also known as q, this is the input of the serial stream into the ESP32
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- mosi - Also known as d, this is the output of the serial stream from the ESP32
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- sclk - Clock signal. Each data bit is clocked out or in on the positive or negative edge of this signal
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- quadwp - Write Protect signal. Only used for 4-bit (qio/qout) transactions.
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- quadhd - Hold signal. Only used for 4-bit (qio/qout) transactions.
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* Device: A SPI slave. Each SPI slave has its own chip select (CS) line, which is made active when
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a transmission to/from the SPI slave occurs.
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* Transaction: One instance of CS going active, data transfer from and/or to a device happening, and
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CS going inactive again. Transactions are atomic, as in they will never be interrupted by another
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transaction.
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SPI transactions
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^^^^^^^^^^^^^^^^
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A transaction on the SPI bus consists of five phases, any of which may be skipped:
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* The command phase. In this phase, a command (0-16 bit) is clocked out.
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* The address phase. In this phase, an address (0-64 bit) is clocked out.
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* The write phase. The master sends data to the slave.
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* The dummy phase. The phase is configurable, used to meet the timing requirements.
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* The read phase. The slave sends data to the master.
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In full duplex, the read and write phases are combined, causing the SPI host to read and
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write data simultaneously. The total transaction length is decided by
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``command_bits + address_bits + trans_conf.length``, while the ``trans_conf.rx_length``
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only determins length of data received into the buffer.
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In half duplex, the length of write phase and read phase are decided by ``trans_conf.length`` and
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``trans_conf.rx_length`` respectively. ** Note that a half duplex transaction with both a read and
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write phase is not supported when using DMA. ** If such transaction is needed, you have to use one
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of the alternative solutions:
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1. use full-duplex mode instead.
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2. disable the DMA by set the last parameter to 0 in bus initialization function just as belows:
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``ret=spi_bus_initialize(VSPI_HOST, &buscfg, 0);``
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this may prohibit you from transmitting and receiving data longer than 32 bytes.
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3. try to use command and address field to replace the write phase.
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The command and address phase are optional in that not every SPI device will need to be sent a command
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and/or address. This is reflected in the device configuration: when the ``command_bits`` or ``address_bits``
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fields are set to zero, no command or address phase is done.
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Something similar is true for the read and write phase: not every transaction needs both data to be written
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as well as data to be read. When ``rx_buffer`` is NULL (and SPI_USE_RXDATA) is not set) the read phase
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is skipped. When ``tx_buffer`` is NULL (and SPI_USE_TXDATA) is not set) the write phase is skipped.
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Using the spi_master driver
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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- Initialize a SPI bus by calling ``spi_bus_initialize``. Make sure to set the correct IO pins in
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the ``bus_config`` struct. Take care to set signals that are not needed to -1.
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- Tell the driver about a SPI slave device connected to the bus by calling spi_bus_add_device.
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Make sure to configure any timing requirements the device has in the ``dev_config`` structure.
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You should now have a handle for the device, to be used when sending it a transaction.
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- To interact with the device, fill one or more spi_transaction_t structure with any transaction
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parameters you need. Either queue all transactions by calling ``spi_device_queue_trans``, later
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quering the result using ``spi_device_get_trans_result``, or handle all requests synchroneously
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by feeding them into ``spi_device_transmit``.
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- Optional: to unload the driver for a device, call ``spi_bus_remove_device`` with the device
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handle as an argument
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- Optional: to remove the driver for a bus, make sure no more drivers are attached and call
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``spi_bus_free``.
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Command and address phases
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^^^^^^^^^^^^^^^^^^^^^^^^^^
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During the command and address phases, ``cmd`` and ``addr`` field in the
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``spi_transaction_t`` struct are sent to the bus, while nothing is read at the
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same time. The default length of command and address phase are set in the
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``spi_device_interface_config_t`` and by ``spi_bus_add_device``. When the the
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flag ``SPI_TRANS_VARIABLE_CMD`` and ``SPI_TRANS_VARIABLE_ADDR`` are not set in
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the ``spi_transaction_t``,the driver automatically set the length of these
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phases to the default value as set when the device is initialized respectively.
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If the length of command and address phases needs to be variable, declare a
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``spi_transaction_ext_t`` descriptor, set the flag ``SPI_TRANS_VARIABLE_CMD``
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or/and ``SPI_TRANS_VARIABLE_ADDR`` in the ``flags`` of ``base`` member and
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configure the rest part of ``base`` as usual. Then the length of each phases
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will be ``command_bits`` and ``address_bits`` set in the ``spi_transaction_ext_t``.
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Write and read phases
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^^^^^^^^^^^^^^^^^^^^^
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Normally, data to be transferred to or from a device will be read from or written to a chunk of memory
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indicated by the ``rx_buffer`` and ``tx_buffer`` members of the transaction structure.
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When DMA is enabled for transfers, these buffers are highly recommended to meet the requirements as belows:
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1. allocated in DMA-capable memory using ``pvPortMallocCaps(size, MALLOC_CAP_DMA)``;
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2. 32-bit aligned (start from the boundary and have length of multiples of 4 bytes).
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If these requirements are not satisfied, efficiency of the transaction will suffer due to the allocation and
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memcpy of temporary buffers.
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Sometimes, the amount of data is very small making it less than optimal allocating a separate buffer
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for it. If the data to be transferred is 32 bits or less, it can be stored in the transaction struct
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itself. For transmitted data, use the ``tx_data`` member for this and set the ``SPI_USE_TXDATA`` flag
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on the transmission. For received data, use ``rx_data`` and set ``SPI_USE_RXDATA``. In both cases, do
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not touch the ``tx_buffer`` or ``rx_buffer`` members, because they use the same memory locations
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as ``tx_data`` and ``rx_data``.
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Application Example
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-------------------
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Display graphics on the 320x240 LCD of WROVER-Kits: :example:`peripherals/spi_master`.
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API Reference - SPI Common
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--------------------------
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.. include:: /_build/inc/spi_common.inc
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API Reference - SPI Master
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--------------------------
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.. include:: /_build/inc/spi_master.inc
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