OVMS3-idf/components/soc
Ivan Grokhotkov e324707cc8 esp_restart: fix possible race while stalling other CPU, enable WDT early
Previously esp_restart would stall the other CPU before enabling RTC_WDT.
If the other CPU was executing an s32c1i instruction, the lock signal
from CPU to the arbiter would still be held after CPU was stalled. If
the CPU running esp_restart would then try to access the same locked
memory pool, it would be stuck, because lock signal would never be
released.

With this change, esp_restart resets the other CPU before stalling it.
Ideally, we would want to reset the CPU and keep it in reset, but the
hardware doesn't have such feature for PRO_CPU (it is possible to hold
APP_CPU in reset using DPORT register). Given that ROM code will not use
s32c1i in the first few hundred cycles, doing reset and then stall seems
to be safe.

In addition to than, RTC_WDT initialization is moved to the beginning of
the function, to prevent possible lock-up if CPU stalling still has any
issue.
2017-11-09 16:05:35 +08:00
..
esp32 esp_restart: fix possible race while stalling other CPU, enable WDT early 2017-11-09 16:05:35 +08:00
test soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
component.mk soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00