91841a53ff
This commit updates the watchdog timers (MWDT and RWDT) in the following ways: - Add seprate LL for MWDT and RWDT. - Add a combined WDT HAL for all Watchdog Timers - Update int_wdt.c and task_wdt.c to use WDT HAL - Remove most dependencies on LL or direct register access in other components. They will now use the WDT HAL - Update use of watchdogs (including RTC WDT) in bootloader and startup code to use the HAL layer.
113 lines
4.6 KiB
C
113 lines
4.6 KiB
C
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include <esp_types.h>
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#include "esp_err.h"
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#include "esp_intr_alloc.h"
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#include "esp_attr.h"
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#include "esp_freertos_hooks.h"
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#include "soc/timer_periph.h"
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#include "driver/timer.h"
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#include "driver/periph_ctrl.h"
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#include "esp_int_wdt.h"
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#include "esp_private/system_internal.h"
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#include "hal/timer_types.h"
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#include "hal/wdt_hal.h"
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#if CONFIG_ESP_INT_WDT
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#define WDT_INT_NUM 24
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#define IWDT_INSTANCE WDT_MWDT1
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#define IWDT_PRESCALER MWDT1_TICK_PRESCALER //Tick period of 500us if WDT source clock is 80MHz
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#define IWDT_TICKS_PER_US MWDT1_TICKS_PER_US
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#define IWDT_INITIAL_TIMEOUT_S 5
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static wdt_hal_context_t iwdt_context;
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//Take care: the tick hook can also be called before esp_int_wdt_init() is called.
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#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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//Not static; the ISR assembly checks this.
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bool int_wdt_app_cpu_ticked = false;
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static void IRAM_ATTR tick_hook(void) {
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if (xPortGetCoreID()!=0) {
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int_wdt_app_cpu_ticked = true;
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} else {
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//Only feed wdt if app cpu also ticked.
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if (int_wdt_app_cpu_ticked) {
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//Todo: Check if there's a way to avoid reconfiguring the stages on each feed.
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wdt_hal_write_protect_disable(&iwdt_context);
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//Reconfigure stage timeouts
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); //Set timeout before interrupt
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2*CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //Set timeout before reset
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wdt_hal_feed(&iwdt_context);
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wdt_hal_write_protect_enable(&iwdt_context);
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int_wdt_app_cpu_ticked = false;
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}
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}
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}
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#else
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static void IRAM_ATTR tick_hook(void) {
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#if CONFIG_IDF_TARGET_ESP32
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if (xPortGetCoreID()!=0) {
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return;
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}
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#endif
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//Todo: Check if there's a way to avoid reconfiguring the stages on each feed.
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wdt_hal_write_protect_disable(&iwdt_context);
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//Reconfigure stage timeouts
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); //Set timeout before interrupt
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2*CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //Set timeout before reset
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wdt_hal_feed(&iwdt_context);
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wdt_hal_write_protect_enable(&iwdt_context);
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}
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#endif
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void esp_int_wdt_init(void) {
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periph_module_enable(PERIPH_TIMG1_MODULE);
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//The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
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//it to their actual value.
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wdt_hal_init(&iwdt_context, IWDT_INSTANCE, IWDT_PRESCALER, true);
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wdt_hal_write_protect_disable(&iwdt_context);
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//The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
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//it to their actual value.
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//1st stage timeout: interrupt
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);
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//2nd stage timeout: reset system
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM);
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//Enable WDT
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wdt_hal_enable(&iwdt_context);
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wdt_hal_write_protect_enable(&iwdt_context);
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}
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void esp_int_wdt_cpu_init(void)
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{
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esp_register_freertos_tick_hook_for_cpu(tick_hook, xPortGetCoreID());
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ESP_INTR_DISABLE(WDT_INT_NUM);
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intr_matrix_set(xPortGetCoreID(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
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//We do not register a handler for the interrupt because it is interrupt level 4 which
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//is not servicable from C. Instead, xtensa_vectors.S has a call to the panic handler for
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//this interrupt.
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ESP_INTR_ENABLE(WDT_INT_NUM);
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}
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#endif
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