This commit updates the watchdog timers (MWDT and RWDT) in the following ways: - Add seprate LL for MWDT and RWDT. - Add a combined WDT HAL for all Watchdog Timers - Update int_wdt.c and task_wdt.c to use WDT HAL - Remove most dependencies on LL or direct register access in other components. They will now use the WDT HAL - Update use of watchdogs (including RTC WDT) in bootloader and startup code to use the HAL layer.
714 lines
26 KiB
C
714 lines
26 KiB
C
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stddef.h>
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#include <sys/lock.h>
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#include <sys/param.h>
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#include "esp_attr.h"
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#include "esp_sleep.h"
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#include "esp_private/esp_timer_private.h"
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#include "esp_log.h"
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#include "esp32/clk.h"
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#include "esp_newlib.h"
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#include "esp_spi_flash.h"
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#include "esp32/rom/cache.h"
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#include "esp32/rom/rtc.h"
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#include "esp32/rom/uart.h"
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#include "soc/cpu.h"
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#include "soc/rtc.h"
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#include "soc/spi_periph.h"
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#include "soc/dport_reg.h"
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#include "soc/soc_memory_layout.h"
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#include "hal/wdt_hal.h"
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#include "driver/rtc_io.h"
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#include "driver/uart.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "sdkconfig.h"
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// If light sleep time is less than that, don't power down flash
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#define FLASH_PD_MIN_SLEEP_TIME_US 2000
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// Time from VDD_SDIO power up to first flash read in ROM code
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#define VDD_SDIO_POWERUP_TO_FLASH_READ_US 700
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// Extra time it takes to enter and exit light sleep and deep sleep
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// For deep sleep, this is until the wake stub runs (not the app).
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#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
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#define LIGHT_SLEEP_TIME_OVERHEAD_US (650 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
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#define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
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#else
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#define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
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#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
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#endif // CONFIG_ESP32_RTC_CLK_SRC
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// Minimal amount of time we can sleep for
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#define LIGHT_SLEEP_MIN_TIME_US 200
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#define CHECK_SOURCE(source, value, mask) ((s_config.wakeup_triggers & mask) && \
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(source == value))
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/**
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* Internal structure which holds all requested deep sleep parameters
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*/
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typedef struct {
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esp_sleep_pd_option_t pd_options[ESP_PD_DOMAIN_MAX];
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uint64_t sleep_duration;
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uint32_t wakeup_triggers : 11;
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uint32_t ext1_trigger_mode : 1;
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uint32_t ext1_rtc_gpio_mask : 18;
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uint32_t ext0_trigger_level : 1;
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uint32_t ext0_rtc_gpio_num : 5;
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uint32_t sleep_time_adjustment;
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uint64_t rtc_ticks_at_sleep_start;
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} sleep_config_t;
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static sleep_config_t s_config = {
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.pd_options = { ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO },
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.wakeup_triggers = 0
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};
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/* Internal variable used to track if light sleep wakeup sources are to be
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expected when determining wakeup cause. */
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static bool s_light_sleep_wakeup = false;
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/* Updating RTC_MEMORY_CRC_REG register via set_rtc_memory_crc()
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is not thread-safe. */
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static _lock_t lock_rtc_memory_crc;
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static const char* TAG = "sleep";
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static uint32_t get_power_down_flags(void);
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static void ext0_wakeup_prepare(void);
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static void ext1_wakeup_prepare(void);
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static void timer_wakeup_prepare(void);
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/* Wake from deep sleep stub
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See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
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*/
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esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
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{
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_lock_acquire(&lock_rtc_memory_crc);
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uint32_t stored_crc = REG_READ(RTC_MEMORY_CRC_REG);
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set_rtc_memory_crc();
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uint32_t calc_crc = REG_READ(RTC_MEMORY_CRC_REG);
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REG_WRITE(RTC_MEMORY_CRC_REG, stored_crc);
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_lock_release(&lock_rtc_memory_crc);
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if(stored_crc != calc_crc) {
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return NULL;
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}
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esp_deep_sleep_wake_stub_fn_t stub_ptr = (esp_deep_sleep_wake_stub_fn_t) REG_READ(RTC_ENTRY_ADDR_REG);
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if (!esp_ptr_executable(stub_ptr)) {
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return NULL;
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}
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return stub_ptr;
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}
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void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)
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{
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_lock_acquire(&lock_rtc_memory_crc);
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REG_WRITE(RTC_ENTRY_ADDR_REG, (uint32_t)new_stub);
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set_rtc_memory_crc();
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_lock_release(&lock_rtc_memory_crc);
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}
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void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) {
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/* Clear MMU for CPU 0 */
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_DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG,
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_DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) | DPORT_PRO_CACHE_MMU_IA_CLR);
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_DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG,
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_DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) & (~DPORT_PRO_CACHE_MMU_IA_CLR));
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#if CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY > 0
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// ROM code has not started yet, so we need to set delay factor
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// used by ets_delay_us first.
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ets_update_cpu_frequency_rom(ets_get_detected_xtal_freq() / 1000000);
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// This delay is configured in menuconfig, it can be used to give
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// the flash chip some time to become ready.
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ets_delay_us(CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY);
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#endif
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}
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void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void);
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void esp_deep_sleep(uint64_t time_in_us)
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{
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esp_sleep_enable_timer_wakeup(time_in_us);
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esp_deep_sleep_start();
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}
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static void IRAM_ATTR flush_uarts(void)
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{
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for (int i = 0; i < 3; ++i) {
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uart_tx_wait_idle(i);
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}
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}
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static void IRAM_ATTR suspend_uarts(void)
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{
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for (int i = 0; i < 3; ++i) {
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REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
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while (REG_GET_FIELD(UART_STATUS_REG(i), UART_ST_UTX_OUT) != 0) {
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;
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}
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}
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}
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static void IRAM_ATTR resume_uarts(void)
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{
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for (int i = 0; i < 3; ++i) {
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REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
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REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
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REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
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}
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}
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static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
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{
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// Stop UART output so that output is not lost due to APB frequency change.
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// For light sleep, suspend UART output — it will resume after wakeup.
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// For deep sleep, wait for the contents of UART FIFO to be sent.
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if (pd_flags & RTC_SLEEP_PD_DIG) {
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flush_uarts();
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} else {
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suspend_uarts();
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}
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// Save current frequency and switch to XTAL
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rtc_cpu_freq_config_t cpu_freq_config;
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rtc_clk_cpu_freq_get_config(&cpu_freq_config);
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rtc_clk_cpu_freq_set_xtal();
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// Configure pins for external wakeup
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if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
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ext0_wakeup_prepare();
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}
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if (s_config.wakeup_triggers & RTC_EXT1_TRIG_EN) {
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ext1_wakeup_prepare();
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}
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// Enable ULP wakeup
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if (s_config.wakeup_triggers & RTC_ULP_TRIG_EN) {
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN);
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}
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// Enter sleep
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rtc_sleep_config_t config = RTC_SLEEP_CONFIG_DEFAULT(pd_flags);
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rtc_sleep_init(config);
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// Configure timer wakeup
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if ((s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) &&
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s_config.sleep_duration > 0) {
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timer_wakeup_prepare();
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}
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uint32_t result = rtc_sleep_start(s_config.wakeup_triggers, 0);
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// Restore CPU frequency
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rtc_clk_cpu_freq_set_config(&cpu_freq_config);
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// re-enable UART output
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resume_uarts();
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return result;
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}
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void IRAM_ATTR esp_deep_sleep_start(void)
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{
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// record current RTC time
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s_config.rtc_ticks_at_sleep_start = rtc_time_get();
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esp_sync_counters_rtc_and_frc();
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// Configure wake stub
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if (esp_get_deep_sleep_wake_stub() == NULL) {
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esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
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}
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// Decide which power domains can be powered down
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uint32_t pd_flags = get_power_down_flags();
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// Correct the sleep time
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s_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US;
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// Enter sleep
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esp_sleep_start(RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO | RTC_SLEEP_PD_XTAL | pd_flags);
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// Because RTC is in a slower clock domain than the CPU, it
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// can take several CPU cycles for the sleep mode to start.
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while (1) {
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;
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}
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}
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/**
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* Helper function which handles entry to and exit from light sleep
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* Placed into IRAM as flash may need some time to be powered on.
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*/
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static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
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uint32_t flash_enable_time_us,
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rtc_vddsdio_config_t vddsdio_config) IRAM_ATTR __attribute__((noinline));
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static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
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uint32_t flash_enable_time_us,
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rtc_vddsdio_config_t vddsdio_config)
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{
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// Enter sleep
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esp_err_t err = esp_sleep_start(pd_flags);
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// If VDDSDIO regulator was controlled by RTC registers before sleep,
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// restore the configuration.
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if (vddsdio_config.force) {
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rtc_vddsdio_set_config(vddsdio_config);
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}
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// If SPI flash was powered down, wait for it to become ready
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if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
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// Wait for the flash chip to start up
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ets_delay_us(flash_enable_time_us);
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}
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return err;
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}
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esp_err_t esp_light_sleep_start(void)
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{
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static portMUX_TYPE light_sleep_lock = portMUX_INITIALIZER_UNLOCKED;
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portENTER_CRITICAL(&light_sleep_lock);
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/* We will be calling esp_timer_private_advance inside DPORT access critical
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* section. Make sure the code on the other CPU is not holding esp_timer
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* lock, otherwise there will be deadlock.
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*/
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esp_timer_private_lock();
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s_config.rtc_ticks_at_sleep_start = rtc_time_get();
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uint64_t frc_time_at_start = esp_timer_get_time();
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DPORT_STALL_OTHER_CPU_START();
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// Decide which power domains can be powered down
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uint32_t pd_flags = get_power_down_flags();
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// Amount of time to subtract from actual sleep time.
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// This is spent on entering and leaving light sleep.
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s_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US;
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// Decide if VDD_SDIO needs to be powered down;
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// If it needs to be powered down, adjust sleep time.
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const uint32_t flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US
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+ CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY;
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#ifndef CONFIG_SPIRAM
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const uint32_t vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US,
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flash_enable_time_us + LIGHT_SLEEP_TIME_OVERHEAD_US + LIGHT_SLEEP_MIN_TIME_US);
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if (s_config.sleep_duration > vddsdio_pd_sleep_duration) {
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pd_flags |= RTC_SLEEP_PD_VDDSDIO;
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s_config.sleep_time_adjustment += flash_enable_time_us;
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}
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#endif //CONFIG_SPIRAM
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rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();
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// Safety net: enable WDT in case exit from light sleep fails
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wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
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bool wdt_was_enabled = wdt_hal_is_enabled(&rtc_wdt_ctx); // If WDT was enabled in the user code, then do not change it here.
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if (!wdt_was_enabled) {
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wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
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uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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wdt_hal_enable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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}
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// Enter sleep, then wait for flash to be ready on wakeup
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esp_err_t err = esp_light_sleep_inner(pd_flags,
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flash_enable_time_us, vddsdio_config);
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s_light_sleep_wakeup = true;
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// FRC1 has been clock gated for the duration of the sleep, correct for that.
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uint64_t rtc_ticks_at_end = rtc_time_get();
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uint64_t frc_time_at_end = esp_timer_get_time();
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uint64_t rtc_time_diff = rtc_time_slowclk_to_us(rtc_ticks_at_end - s_config.rtc_ticks_at_sleep_start,
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esp_clk_slowclk_cal_get());
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uint64_t frc_time_diff = frc_time_at_end - frc_time_at_start;
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int64_t time_diff = rtc_time_diff - frc_time_diff;
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/* Small negative values (up to 1 RTC_SLOW clock period) are possible,
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* for very small values of sleep_duration. Ignore those to keep esp_timer
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* monotonic.
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*/
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if (time_diff > 0) {
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esp_timer_private_advance(time_diff);
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}
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esp_set_time_from_rtc();
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esp_timer_private_unlock();
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DPORT_STALL_OTHER_CPU_END();
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if (!wdt_was_enabled) {
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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}
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portEXIT_CRITICAL(&light_sleep_lock);
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return err;
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}
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esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
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{
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// For most of sources it is enough to set trigger mask in local
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// configuration structure. The actual RTC wake up options
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// will be updated by esp_sleep_start().
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if (source == ESP_SLEEP_WAKEUP_ALL) {
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s_config.wakeup_triggers = 0;
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} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TIMER, RTC_TIMER_TRIG_EN)) {
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s_config.wakeup_triggers &= ~RTC_TIMER_TRIG_EN;
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s_config.sleep_duration = 0;
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} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_EXT0, RTC_EXT0_TRIG_EN)) {
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s_config.ext0_rtc_gpio_num = 0;
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s_config.ext0_trigger_level = 0;
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s_config.wakeup_triggers &= ~RTC_EXT0_TRIG_EN;
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} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_EXT1, RTC_EXT1_TRIG_EN)) {
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s_config.ext1_rtc_gpio_mask = 0;
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s_config.ext1_trigger_mode = 0;
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s_config.wakeup_triggers &= ~RTC_EXT1_TRIG_EN;
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} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TOUCHPAD, RTC_TOUCH_TRIG_EN)) {
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s_config.wakeup_triggers &= ~RTC_TOUCH_TRIG_EN;
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} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_GPIO, RTC_GPIO_TRIG_EN)) {
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s_config.wakeup_triggers &= ~RTC_GPIO_TRIG_EN;
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} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_UART, (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN))) {
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s_config.wakeup_triggers &= ~(RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN);
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}
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#ifdef CONFIG_ESP32_ULP_COPROC_ENABLED
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else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_ULP, RTC_ULP_TRIG_EN)) {
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s_config.wakeup_triggers &= ~RTC_ULP_TRIG_EN;
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}
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#endif
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else {
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ESP_LOGE(TAG, "Incorrect wakeup source (%d) to disable.", (int) source);
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return ESP_ERR_INVALID_STATE;
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}
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return ESP_OK;
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}
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esp_err_t esp_sleep_enable_ulp_wakeup(void)
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{
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#ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
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return ESP_ERR_NOT_SUPPORTED;
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#endif
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#ifdef CONFIG_ESP32_ULP_COPROC_ENABLED
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if(s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
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ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
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|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
s_config.wakeup_triggers |= RTC_ULP_TRIG_EN;
|
|
return ESP_OK;
|
|
#else
|
|
return ESP_ERR_INVALID_STATE;
|
|
#endif
|
|
}
|
|
|
|
esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us)
|
|
{
|
|
s_config.wakeup_triggers |= RTC_TIMER_TRIG_EN;
|
|
s_config.sleep_duration = time_in_us;
|
|
return ESP_OK;
|
|
}
|
|
|
|
static void timer_wakeup_prepare(void)
|
|
{
|
|
uint32_t period = esp_clk_slowclk_cal_get();
|
|
int64_t sleep_duration = (int64_t) s_config.sleep_duration - (int64_t) s_config.sleep_time_adjustment;
|
|
if (sleep_duration < 0) {
|
|
sleep_duration = 0;
|
|
}
|
|
int64_t rtc_count_delta = rtc_time_us_to_slowclk(sleep_duration, period);
|
|
|
|
rtc_sleep_set_wakeup_time(s_config.rtc_ticks_at_sleep_start + rtc_count_delta);
|
|
}
|
|
|
|
esp_err_t esp_sleep_enable_touchpad_wakeup(void)
|
|
{
|
|
#ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
|
|
return ESP_ERR_NOT_SUPPORTED;
|
|
#endif
|
|
if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) {
|
|
ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
s_config.wakeup_triggers |= RTC_TOUCH_TRIG_EN;
|
|
return ESP_OK;
|
|
}
|
|
|
|
touch_pad_t esp_sleep_get_touchpad_wakeup_status(void)
|
|
{
|
|
if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_TOUCHPAD) {
|
|
return TOUCH_PAD_MAX;
|
|
}
|
|
touch_pad_t pad_num;
|
|
esp_err_t ret = touch_pad_get_wakeup_status(&pad_num);
|
|
assert(ret == ESP_OK && "wakeup reason is RTC_TOUCH_TRIG_EN but SENS_TOUCH_MEAS_EN is zero");
|
|
return pad_num;
|
|
}
|
|
|
|
esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
|
|
{
|
|
if (level < 0 || level > 1) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
if (!RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
|
|
ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP");
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
s_config.ext0_rtc_gpio_num = rtc_io_number_get(gpio_num);
|
|
s_config.ext0_trigger_level = level;
|
|
s_config.wakeup_triggers |= RTC_EXT0_TRIG_EN;
|
|
return ESP_OK;
|
|
}
|
|
|
|
static void ext0_wakeup_prepare(void)
|
|
{
|
|
int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
|
|
// Set GPIO to be used for wakeup
|
|
REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtc_gpio_num);
|
|
// Set level which will trigger wakeup
|
|
SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
|
|
s_config.ext0_trigger_level, RTC_CNTL_EXT_WAKEUP0_LV_S);
|
|
// Find GPIO descriptor in the rtc_io_desc table and configure the pad
|
|
const rtc_io_desc_t* desc = &rtc_io_desc[rtc_gpio_num];
|
|
REG_SET_BIT(desc->reg, desc->mux);
|
|
SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func);
|
|
REG_SET_BIT(desc->reg, desc->ie);
|
|
}
|
|
|
|
esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode_t mode)
|
|
{
|
|
if (mode > ESP_EXT1_WAKEUP_ANY_HIGH) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
// Translate bit map of GPIO numbers into the bit map of RTC IO numbers
|
|
uint32_t rtc_gpio_mask = 0;
|
|
for (int gpio = 0; mask; ++gpio, mask >>= 1) {
|
|
if ((mask & 1) == 0) {
|
|
continue;
|
|
}
|
|
if (!RTC_GPIO_IS_VALID_GPIO(gpio)) {
|
|
ESP_LOGE(TAG, "Not an RTC IO: GPIO%d", gpio);
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
rtc_gpio_mask |= BIT(rtc_io_number_get(gpio));
|
|
}
|
|
s_config.ext1_rtc_gpio_mask = rtc_gpio_mask;
|
|
s_config.ext1_trigger_mode = mode;
|
|
s_config.wakeup_triggers |= RTC_EXT1_TRIG_EN;
|
|
return ESP_OK;
|
|
}
|
|
|
|
static void ext1_wakeup_prepare(void)
|
|
{
|
|
// Configure all RTC IOs selected as ext1 wakeup inputs
|
|
uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask;
|
|
for (int gpio = 0; gpio < GPIO_PIN_COUNT && rtc_gpio_mask != 0; ++gpio) {
|
|
int rtc_pin = rtc_io_number_get(gpio);
|
|
if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) {
|
|
continue;
|
|
}
|
|
const rtc_io_desc_t* desc = &rtc_io_desc[rtc_pin];
|
|
// Route pad to RTC
|
|
REG_SET_BIT(desc->reg, desc->mux);
|
|
SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func);
|
|
// set input enable in sleep mode
|
|
REG_SET_BIT(desc->reg, desc->ie);
|
|
// Pad configuration depends on RTC_PERIPH state in sleep mode
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) {
|
|
// RTC_PERIPH will be powered down, so RTC_IO_ registers will
|
|
// loose their state. Lock pad configuration.
|
|
// Pullups/pulldowns also need to be disabled.
|
|
REG_CLR_BIT(desc->reg, desc->pulldown);
|
|
REG_CLR_BIT(desc->reg, desc->pullup);
|
|
REG_SET_BIT(RTC_CNTL_HOLD_FORCE_REG, desc->hold_force);
|
|
}
|
|
// Keep track of pins which are processed to bail out early
|
|
rtc_gpio_mask &= ~BIT(rtc_pin);
|
|
}
|
|
// Clear state from previous wakeup
|
|
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
|
|
// Set pins to be used for wakeup
|
|
REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, s_config.ext1_rtc_gpio_mask);
|
|
// Set logic function (any low, all high)
|
|
SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
|
|
s_config.ext1_trigger_mode, RTC_CNTL_EXT_WAKEUP1_LV_S);
|
|
}
|
|
|
|
uint64_t esp_sleep_get_ext1_wakeup_status(void)
|
|
{
|
|
if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_EXT1) {
|
|
return 0;
|
|
}
|
|
uint32_t status = REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS);
|
|
// Translate bit map of RTC IO numbers into the bit map of GPIO numbers
|
|
uint64_t gpio_mask = 0;
|
|
for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) {
|
|
if (!RTC_GPIO_IS_VALID_GPIO(gpio)) {
|
|
continue;
|
|
}
|
|
int rtc_pin = rtc_io_number_get(gpio);
|
|
if ((status & BIT(rtc_pin)) == 0) {
|
|
continue;
|
|
}
|
|
gpio_mask |= 1ULL << gpio;
|
|
}
|
|
return gpio_mask;
|
|
}
|
|
|
|
esp_err_t esp_sleep_enable_gpio_wakeup(void)
|
|
{
|
|
if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
|
|
ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP");
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
s_config.wakeup_triggers |= RTC_GPIO_TRIG_EN;
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t esp_sleep_enable_uart_wakeup(int uart_num)
|
|
{
|
|
if (uart_num == UART_NUM_0) {
|
|
s_config.wakeup_triggers |= RTC_UART0_TRIG_EN;
|
|
} else if (uart_num == UART_NUM_1) {
|
|
s_config.wakeup_triggers |= RTC_UART1_TRIG_EN;
|
|
} else {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
|
|
{
|
|
if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET && !s_light_sleep_wakeup) {
|
|
return ESP_SLEEP_WAKEUP_UNDEFINED;
|
|
}
|
|
|
|
uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);
|
|
if (wakeup_cause & RTC_EXT0_TRIG_EN) {
|
|
return ESP_SLEEP_WAKEUP_EXT0;
|
|
} else if (wakeup_cause & RTC_EXT1_TRIG_EN) {
|
|
return ESP_SLEEP_WAKEUP_EXT1;
|
|
} else if (wakeup_cause & RTC_TIMER_TRIG_EN) {
|
|
return ESP_SLEEP_WAKEUP_TIMER;
|
|
} else if (wakeup_cause & RTC_TOUCH_TRIG_EN) {
|
|
return ESP_SLEEP_WAKEUP_TOUCHPAD;
|
|
} else if (wakeup_cause & RTC_ULP_TRIG_EN) {
|
|
return ESP_SLEEP_WAKEUP_ULP;
|
|
} else if (wakeup_cause & RTC_GPIO_TRIG_EN) {
|
|
return ESP_SLEEP_WAKEUP_GPIO;
|
|
} else if (wakeup_cause & (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN)) {
|
|
return ESP_SLEEP_WAKEUP_UART;
|
|
} else {
|
|
return ESP_SLEEP_WAKEUP_UNDEFINED;
|
|
}
|
|
}
|
|
|
|
esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
|
|
esp_sleep_pd_option_t option)
|
|
{
|
|
if (domain >= ESP_PD_DOMAIN_MAX || option > ESP_PD_OPTION_AUTO) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
s_config.pd_options[domain] = option;
|
|
return ESP_OK;
|
|
}
|
|
|
|
static uint32_t get_power_down_flags(void)
|
|
{
|
|
// Where needed, convert AUTO options to ON. Later interpret AUTO as OFF.
|
|
|
|
// RTC_SLOW_MEM is needed for the ULP, so keep RTC_SLOW_MEM powered up if ULP
|
|
// is used and RTC_SLOW_MEM is Auto.
|
|
// If there is any data placed into .rtc.data or .rtc.bss segments, and
|
|
// RTC_SLOW_MEM is Auto, keep it powered up as well.
|
|
|
|
// Labels are defined in the linker script, see esp32.ld.
|
|
extern int _rtc_slow_length;
|
|
|
|
if ((s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] == ESP_PD_OPTION_AUTO) &&
|
|
((size_t) &_rtc_slow_length > 0 ||
|
|
(s_config.wakeup_triggers & RTC_ULP_TRIG_EN))) {
|
|
s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] = ESP_PD_OPTION_ON;
|
|
}
|
|
|
|
// RTC_FAST_MEM is needed for deep sleep stub.
|
|
// If RTC_FAST_MEM is Auto, keep it powered on, so that deep sleep stub
|
|
// can run.
|
|
// In the new chip revision, deep sleep stub will be optional,
|
|
// and this can be changed.
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] == ESP_PD_OPTION_AUTO) {
|
|
s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON;
|
|
}
|
|
|
|
// RTC_PERIPH is needed for EXT0 wakeup and GPIO wakeup.
|
|
// If RTC_PERIPH is auto, and EXT0/GPIO aren't enabled, power down RTC_PERIPH.
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) {
|
|
if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN | RTC_GPIO_TRIG_EN)) {
|
|
s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON;
|
|
} else if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
|
|
// In both rev. 0 and rev. 1 of ESP32, forcing power up of RTC_PERIPH
|
|
// prevents ULP timer and touch FSMs from working correctly.
|
|
s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF;
|
|
}
|
|
}
|
|
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] == ESP_PD_OPTION_AUTO) {
|
|
s_config.pd_options[ESP_PD_DOMAIN_XTAL] = ESP_PD_OPTION_OFF;
|
|
}
|
|
|
|
const char* option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */};
|
|
ESP_LOGD(TAG, "RTC_PERIPH: %s, RTC_SLOW_MEM: %s, RTC_FAST_MEM: %s",
|
|
option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH]],
|
|
option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM]],
|
|
option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM]]);
|
|
|
|
// Prepare flags based on the selected options
|
|
uint32_t pd_flags = 0;
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON) {
|
|
pd_flags |= RTC_SLEEP_PD_RTC_FAST_MEM;
|
|
}
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] != ESP_PD_OPTION_ON) {
|
|
pd_flags |= RTC_SLEEP_PD_RTC_SLOW_MEM;
|
|
}
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) {
|
|
pd_flags |= RTC_SLEEP_PD_RTC_PERIPH;
|
|
}
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] != ESP_PD_OPTION_ON) {
|
|
pd_flags |= RTC_SLEEP_PD_XTAL;
|
|
}
|
|
|
|
if ((s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) == 0) {
|
|
// If enabled EXT1 only and enable the additional current by touch, should be keep RTC_PERIPH power on.
|
|
#if ((defined CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) && (defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT))
|
|
pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
|
|
#endif
|
|
}
|
|
return pd_flags;
|
|
}
|
|
|
|
void esp_deep_sleep_disable_rom_logging(void)
|
|
{
|
|
/* To disable logging in the ROM, only the least significant bit of the register is used,
|
|
* but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
|
|
* you need to write to this register in the same format.
|
|
* Namely, the upper 16 bits and lower should be the same.
|
|
*/
|
|
REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
|
|
}
|