101 lines
3.6 KiB
Plaintext
101 lines
3.6 KiB
Plaintext
menu "Example Configuration"
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choice PHY_MODEL
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prompt "Ethernet PHY Device"
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default PHY_IP101
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help
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Select the PHY driver to use for the example.
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config PHY_IP101
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bool "IP101"
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help
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IP101 is a single port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver.
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Goto http://www.icplus.com.tw/pp-IP101G.html for more information about it.
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config PHY_TLK110
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bool "TLK110"
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help
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TLK110 is an Industrial 10/100Mbps Ethernet Physical Layer Transceiver.
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Goto http://www.ti.com/product/TLK110 for information about it.
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config PHY_LAN8720
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bool "LAN8720"
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help
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LAN8720 is a small footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support.
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Goto https://www.microchip.com/LAN8720A for more information about it.
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endchoice
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config PHY_ADDRESS
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int "Ethernet PHY Address"
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default 1
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range 0 31
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help
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PHY Address of your PHY device. It dependens on your schematic design.
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choice PHY_CLOCK_MODE
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prompt "Ethernet PHY Clock Mode"
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default PHY_CLOCK_GPIO0_IN
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help
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Select external (input on GPIO0) or internal (output on GPIO0, GPIO16 or GPIO17) RMII clock.
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config PHY_CLOCK_GPIO0_IN
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bool "GPIO0 Input"
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help
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Input of 50MHz RMII clock on GPIO0.
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config PHY_CLOCK_GPIO0_OUT
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bool "GPIO0 Output(READ HELP)"
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help
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GPIO0 can be set to output a pre-divided PLL clock (test only!).
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Enabling this option will configure GPIO0 to output a 50MHz clock.
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In fact this clock doesn't have directly relationship with EMAC peripheral.
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Sometimes this clock won't work well with your PHY chip. You might need to
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add some extra devices after GPIO0 (e.g. inverter).
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Note that outputting RMII clock on GPIO0 is an experimental practice.
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If you want the Ethernet to work with WiFi, don't select GPIO0 output mode for stability.
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config PHY_CLOCK_GPIO16_OUT
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bool "GPIO16 Output"
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help
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Output the internal 50MHz RMII clock on GPIO16.
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config PHY_CLOCK_GPIO17_OUT
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bool "GPIO17 Output (inverted)"
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help
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Output the internal 50MHz RMII clock on GPIO17 (inverted signal).
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endchoice
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config PHY_CLOCK_MODE
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int
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default 0 if PHY_CLOCK_GPIO0_IN
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default 1 if PHY_CLOCK_GPIO0_OUT
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default 2 if PHY_CLOCK_GPIO16_OUT
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default 3 if PHY_CLOCK_GPIO17_OUT
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config PHY_USE_POWER_PIN
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bool "Use PHY Power (enable / disable) pin"
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default y
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help
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Use a GPIO "power pin" to power the PHY on/off during operation.
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When using GPIO0 to input RMII clock, the reset process will be interfered by this clock.
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So we need another GPIO to control the switch on / off of the RMII clock.
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if PHY_USE_POWER_PIN
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config PHY_POWER_PIN
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int "PHY Power GPIO"
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default 5
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range 0 33
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depends on PHY_USE_POWER_PIN
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help
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GPIO number to use for powering on/off the PHY.
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endif
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config PHY_SMI_MDC_PIN
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int "SMI MDC Pin Number"
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default 23
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range 0 33
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help
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GPIO number used for SMI clock signal.
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config PHY_SMI_MDIO_PIN
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int "SMI MDIO Pin Number"
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default 18
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range 0 33
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help
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GPIO number used for SMI data signal.
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endmenu
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