964f5a91f7
If zero-overhead loop buffer is enabled, under certain rare conditions when executing a zero-overhead loop, the CPU may attempt to execute an invalid instruction. Work around by disabling the buffer.
113 lines
3.2 KiB
C
113 lines
3.2 KiB
C
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_CPU_H
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#define _SOC_CPU_H
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include "xtensa/corebits.h"
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#include "xtensa/config/core.h"
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/* C macros for xtensa special register read/write/exchange */
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#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval));
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#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval));
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#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval));
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/** @brief Read current stack pointer address
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*
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*/
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static inline void *get_sp()
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{
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void *sp;
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asm volatile ("mov %0, sp;" : "=r" (sp));
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return sp;
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}
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/* Functions to set page attributes for Region Protection option in the CPU.
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* See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
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*/
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static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
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{
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asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
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}
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static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
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{
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asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
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}
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static inline void cpu_init_memctl()
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{
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#if XCHAL_ERRATUM_572
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uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
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WSR(MEMCTL, memctl);
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#endif // XCHAL_ERRATUM_572
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}
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/**
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* @brief Configure memory region protection
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*
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* Make page 0 access raise an exception.
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* Also protect some other unused pages so we can catch weirdness.
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* Useful attribute values:
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* 0 — cached, RW
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* 2 — bypass cache, RWX (default value after CPU reset)
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* 15 — no access, raise exception
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*/
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static inline void cpu_configure_region_protection()
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{
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const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
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for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
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cpu_write_dtlb(pages_to_protect[i], 0xf);
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cpu_write_itlb(pages_to_protect[i], 0xf);
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}
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cpu_write_dtlb(0x20000000, 0);
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cpu_write_itlb(0x20000000, 0);
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}
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/**
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* @brief Stall CPU using RTC controller
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* @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
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*/
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void esp_cpu_stall(int cpu_id);
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/**
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* @brief Un-stall CPU using RTC controller
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* @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
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*/
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void esp_cpu_unstall(int cpu_id);
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/**
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* @brief Reset CPU using RTC controller
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* @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
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*/
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void esp_cpu_reset(int cpu_id);
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/**
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* @brief Returns true if a JTAG debugger is attached to CPU
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* OCD (on chip debug) port.
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*
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* @note If "Make exception and panic handlers JTAG/OCD aware"
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* is disabled, this function always returns false.
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*/
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bool esp_cpu_in_ocd_debug_mode();
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#endif
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