90bbcbcdc0
- libsodium: silence warnings - unit tests: fix warnings - spiram: fix warnings - ringbuf test: enable by default, reduce delays
133 lines
3.8 KiB
C
133 lines
3.8 KiB
C
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#include <esp_types.h>
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#include <stdio.h>
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#include "rom/ets_sys.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/xtensa_api.h"
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#include "unity.h"
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#include "soc/uart_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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/*
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This test tests the 'fast' peripherial bus at 0x3ff40000. This bus is connected directly to the core, and as such
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can receive 'speculative' reads, that is, reads that may or may not actually be executed in the code flow. This
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may mess with any FIFOs mapped in the region: if a byte gets dropped due to a missed speculative read, the fifo
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may advance to the next byte anyway.
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This code tests reading/writing from the UART1 FIFO, using both cores. For this to work, it's required that the
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UARTs RX and TX lines are connected.
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*/
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void test_fastbus_cp(int fifo_addr, unsigned char *buf, int len, int *dummy);
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static volatile int state = 0;
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static volatile int xor = 0;
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static unsigned char res[128];
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static void tskOne(void *pvParameters)
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{
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int run = 0, err = 0;
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int x;
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int ct[256];
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volatile int w;
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int dummy;
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while (1) {
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state = 1;
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for (x = 0; x < 64; x++) {
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WRITE_PERI_REG(UART_FIFO_REG(1), x ^ xor);
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}
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for (w = 0; w < (1 << 14); w++); //delay
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state = 2;
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test_fastbus_cp(UART_FIFO_REG(1), &res[0], 64, &dummy);
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for (w = 0; w < (1 << 10); w++); //delay
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for (x = 0; x < 255; x++) {
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ct[x] = 0; //zero ctrs
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}
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for (x = 0; x < 128; x++) {
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ct[(int)res[x]^xor]++; //count values
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}
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for (x = 0; x < 255; x++) { //check counts
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if (ct[x] != (x < 128 ? 1 : 0)) {
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//Disregard first few loops; there may be crap in the fifo.
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if (run > 2) {
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err++;
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printf("Error! Received value %d %d times!\n", x, ct[x]);
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}
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}
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}
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run++;
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if ((run & 255) == 0) {
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printf("Loop %d errct %d\n", run, err);
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}
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xor = (xor + 1) & 0xff;
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}
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}
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#define FB2ADDR 0x40098000
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static void tskTwo(void *pvParameters)
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{
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int x;
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int dummy;
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int *p = (int *)FB2ADDR;
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int *s = (int *)test_fastbus_cp;
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for (x = 0; x < 100; x++) {
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*p++ = *s++;
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}
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void (*test_fastbus_cp2)(int fifo_addr, unsigned char * buf, int len, int * dummy) = (void *)FB2ADDR;
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while (1) {
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while (state != 1) ;
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for (x = 64; x < 128; x++) {
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WRITE_PERI_REG(UART_FIFO_REG(1), x ^ xor);
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}
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while (state != 2);
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test_fastbus_cp2(UART_FIFO_REG(1), &res[64], 64, &dummy);
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}
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}
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// TODO: split this thing into separate orthogonal tests
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TEST_CASE("Fast I/O bus test", "[hw][ignore]")
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{
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int i;
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if ((REG_UART_BASE(0) >> 16) != 0x3ff4) {
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printf("Error! Uart base isn't on fast bus.\n");
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TEST_ASSERT(0);
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}
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gpio_pullup_dis(10);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, FUNC_SD_DATA2_U1RXD);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, FUNC_SD_DATA3_U1TXD);
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int reg_val = (1 << UART_RXFIFO_FULL_THRHD_S);
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WRITE_PERI_REG(UART_CONF1_REG(1), reg_val);
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WRITE_PERI_REG(UART_CLKDIV_REG(1), 0x30); //semi-random
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// CLEAR_PERI_REG_MASK(UART_INT_ENA_REG(1), UART_TXFIFO_EMPTY_INT_ENA|UART_RXFIFO_TOUT_INT_ENA);
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TaskHandle_t th[2];
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printf("Creating tasks\n");
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xTaskCreatePinnedToCore(tskOne , "tskone" , 2048, NULL, 3, &th[0], 0);
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xTaskCreatePinnedToCore(tskTwo , "tsktwo" , 2048, NULL, 3, &th[1], 1);
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// Let stuff run for 20s
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while (1) {
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vTaskDelay(20000 / portTICK_PERIOD_MS);
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}
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//Shut down all the tasks
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for (i = 0; i < 2; i++) {
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vTaskDelete(th[i]);
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}
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xt_ints_off(1 << ETS_UART0_INUM);
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}
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