31dac92e5f
OpenCores Ethernet MAC has a relatively simple interface, and is already supported in QEMU. This makes it a good candidate for enabling network support when running IDF apps in QEMU, compared to the relatively more complex task of writing a QEMU model of ESP32 EMAC. This driver is written with QEMU in mind: it does not implement or handle things that aren't implemented or handled in the QEMU model: error flags, error interrupts. The transmit part of the driver also assumes that the TX operation is done immediately when the TX descriptor is written (which is the case with QEMU), hence waiting for the TX operation to complete is not necessary. For simplicity, the driver assumes that the peripheral register occupy the same memory range as the ESP32 EMAC registers, and the same interrupt source number is used.
180 lines
6.3 KiB
Text
180 lines
6.3 KiB
Text
menu "Ethernet"
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menuconfig ETH_USE_ESP32_EMAC
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depends on IDF_TARGET_ESP32
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bool "Support ESP32 internal EMAC controller"
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default y
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help
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ESP32 integrates a 10/100M Ethernet MAC controller.
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if ETH_USE_ESP32_EMAC
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choice ETH_PHY_INTERFACE
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prompt "PHY interface"
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default ETH_PHY_INTERFACE_RMII
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help
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Select the communication interface between MAC and PHY chip.
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config ETH_PHY_INTERFACE_RMII
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bool "Reduced Media Independent Interface (RMII)"
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config ETH_PHY_INTERFACE_MII
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bool "Media Independent Interface (MII)"
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endchoice
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if ETH_PHY_INTERFACE_RMII
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choice ETH_RMII_CLK_MODE
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prompt "RMII clock mode"
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default ETH_RMII_CLK_INPUT
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help
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Select external or internal RMII clock.
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config ETH_RMII_CLK_INPUT
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bool "Input RMII clock from external"
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help
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MAC will get RMII clock from outside.
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Note that ESP32 only supports GPIO0 to input the RMII clock.
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config ETH_RMII_CLK_OUTPUT
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bool "Output RMII clock from internal"
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help
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ESP32 can generate RMII clock by internal APLL.
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This clock can be routed to the external PHY device.
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ESP32 supports to route the RMII clock to GPIO0/16/17.
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endchoice
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endif
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if ETH_RMII_CLK_INPUT
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config ETH_RMII_CLK_IN_GPIO
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int
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range 0 0
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default 0
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help
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ESP32 only supports GPIO0 to input the RMII clock.
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endif
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if ETH_RMII_CLK_OUTPUT
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config ETH_RMII_CLK_OUTPUT_GPIO0
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bool "Output RMII clock from GPIO0 (Experimental!)"
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default n
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help
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GPIO0 can be set to output a pre-divided PLL clock (test only!).
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Enabling this option will configure GPIO0 to output a 50MHz clock.
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In fact this clock doesn't have directly relationship with EMAC peripheral.
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Sometimes this clock won't work well with your PHY chip. You might need to
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add some extra devices after GPIO0 (e.g. inverter).
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Note that outputting RMII clock on GPIO0 is an experimental practice.
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If you want the Ethernet to work with WiFi, don't select GPIO0 output mode for stability.
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if !ETH_RMII_CLK_OUTPUT_GPIO0
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config ETH_RMII_CLK_OUT_GPIO
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int "RMII clock GPIO number"
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range 16 17
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default 17
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help
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Set the GPIO number to output RMII Clock.
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endif
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endif
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config ETH_SMI_MDC_GPIO
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int "SMI MDC GPIO number"
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default 23
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range 0 33
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help
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Set the GPIO number used by SMI MDC.
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config ETH_SMI_MDIO_GPIO
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int "SMI MDIO GPIO number"
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default 18
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range 0 33
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help
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Set the GPIO number used by SMI MDIO.
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config ETH_PHY_USE_RST
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bool "Use Reset Pin of PHY Chip"
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default y
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help
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Set this option to true if you want to control PHY chip's reset using a GPIO.
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Check the schematic of you board to make sure if it's necessary to use this feature.
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if ETH_PHY_USE_RST
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config ETH_PHY_RST_GPIO
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int "PHY RST GPIO number"
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default 5
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range 0 33
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help
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Set the GPIO number used by the PHY chip's RST pin.
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endif
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config ETH_DMA_BUFFER_SIZE
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int "Ethernet DMA buffer size (Byte)"
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range 256 1600
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default 512
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help
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Set the size of each buffer used by Ethernet MAC DMA.
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config ETH_DMA_RX_BUFFER_NUM
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int "Amount of Ethernet DMA Rx buffers"
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range 3 30
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default 10
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help
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Number of DMA receive buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE.
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Larger number of buffers could increase throughput somehow.
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config ETH_DMA_TX_BUFFER_NUM
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int "Amount of Ethernet DMA Tx buffers"
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range 3 30
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default 10
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help
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Number of DMA transmit buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE.
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Larger number of buffers could increase throughput somehow.
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endif
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menuconfig ETH_USE_SPI_ETHERNET
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bool "Support SPI to Ethernet Module"
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default y
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help
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ESP-IDF can also support some SPI-Ethernet module.
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if ETH_USE_SPI_ETHERNET
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menuconfig ETH_SPI_ETHERNET_DM9051
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bool "Use DM9051"
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default y
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help
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DM9051 is a fast Ethernet controller with an SPI interface.
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It's also integrated with a 10/100M PHY and MAC.
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Set true to enable DM9051 driver.
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if ETH_SPI_ETHERNET_DM9051
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config ETH_DM9051_INT_GPIO
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int "DM9051 Interrupt GPIO number"
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default 4
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range 0 33
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help
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Set the GPIO number used by DM9051's Interrupt pin.
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endif
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endif
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menuconfig ETH_USE_OPENETH
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bool "Support OpenCores Ethernet MAC (for use with QEMU)"
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default n
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help
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OpenCores Ethernet MAC driver can be used when an ESP-IDF application
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is executed in QEMU. This driver is not supported when running on a
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real chip.
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if ETH_USE_OPENETH
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config ETH_OPENETH_DMA_RX_BUFFER_NUM
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int "Number of Ethernet DMA Rx buffers"
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range 1 64
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default 4
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help
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Number of DMA receive buffers, each buffer is 1600 bytes.
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config ETH_OPENETH_DMA_TX_BUFFER_NUM
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int "Number of Ethernet DMA Tx buffers"
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range 1 64
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default 1
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help
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Number of DMA transmit buffers, each buffer is 1600 bytes.
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endif
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endmenu
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