687 lines
23 KiB
C
687 lines
23 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include <xtensa/config/core.h>
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#include "esp32s2/rom/rtc.h"
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#include "esp32s2/rom/uart.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/xtensa_api.h"
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#include "soc/uart_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/extmem_reg.h"
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#include "soc/cache_memory.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/timer_group_struct.h"
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#include "soc/timer_group_reg.h"
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#include "soc/cpu.h"
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#include "soc/soc_memory_layout.h"
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#include "soc/rtc.h"
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#include "soc/rtc_wdt.h"
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#include "esp_private/gdbstub.h"
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#include "esp_debug_helpers.h"
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#include "esp_private/panic_reason.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_core_dump.h"
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#include "esp_spi_flash.h"
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#include "esp32s2/cache_err_int.h"
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#include "esp_app_trace.h"
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#include "esp_private/system_internal.h"
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#include "sdkconfig.h"
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#if CONFIG_SYSVIEW_ENABLE
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#include "SEGGER_RTT.h"
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#endif
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#if CONFIG_APPTRACE_ONPANIC_HOST_FLUSH_TMO == -1
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#define APPTRACE_ONPANIC_HOST_FLUSH_TMO ESP_APPTRACE_TMO_INFINITE
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#else
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#define APPTRACE_ONPANIC_HOST_FLUSH_TMO (1000*CONFIG_APPTRACE_ONPANIC_HOST_FLUSH_TMO)
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#endif
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/*
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Panic handlers; these get called when an unhandled exception occurs or the assembly-level
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task switching / interrupt code runs into an unrecoverable error. The default task stack
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overflow handler and abort handler are also in here.
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*/
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/*
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Note: The linker script will put everything in this file in IRAM/DRAM, so it also works with flash cache disabled.
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*/
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#if !CONFIG_ESP32S2_PANIC_SILENT_REBOOT
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//printf may be broken, so we fix our own printing fns...
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static void panicPutChar(char c)
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{
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while (((READ_PERI_REG(UART_STATUS_REG(CONFIG_ESP_CONSOLE_UART_NUM)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT) >= 126) ;
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WRITE_PERI_REG(UART_FIFO_AHB_REG(CONFIG_ESP_CONSOLE_UART_NUM), c);
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}
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static void panicPutStr(const char *c)
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{
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int x = 0;
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while (c[x] != 0) {
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panicPutChar(c[x]);
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x++;
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}
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}
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static void panicPutHex(int a)
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{
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int x;
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int c;
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for (x = 0; x < 8; x++) {
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c = (a >> 28) & 0xf;
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if (c < 10) {
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panicPutChar('0' + c);
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} else {
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panicPutChar('a' + c - 10);
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}
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a <<= 4;
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}
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}
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static void panicPutDec(int a)
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{
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int n1, n2;
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n1 = a % 10;
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n2 = a / 10;
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if (n2 == 0) {
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panicPutChar(' ');
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} else {
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panicPutChar(n2 + '0');
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}
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panicPutChar(n1 + '0');
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}
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#else
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//No printing wanted. Stub out these functions.
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static void panicPutChar(char c) { }
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static void panicPutStr(const char *c) { }
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static void panicPutHex(int a) { }
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static void panicPutDec(int a) { }
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#endif
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void __attribute__((weak)) vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName )
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{
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panicPutStr("***ERROR*** A stack overflow in task ");
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panicPutStr((char *)pcTaskName);
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panicPutStr(" has been detected.\r\n");
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abort();
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}
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/* These two weak stubs for esp_reset_reason_{get,set}_hint are used when
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* the application does not call esp_reset_reason() function, and
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* reset_reason.c is not linked into the output file.
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*/
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void __attribute__((weak)) esp_reset_reason_set_hint(esp_reset_reason_t hint)
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{
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}
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esp_reset_reason_t __attribute__((weak)) esp_reset_reason_get_hint(void)
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{
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return ESP_RST_UNKNOWN;
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}
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static bool abort_called;
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static __attribute__((noreturn)) inline void invoke_abort(void)
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{
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abort_called = true;
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#if CONFIG_APPTRACE_ENABLE
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#if CONFIG_SYSVIEW_ENABLE
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SEGGER_RTT_ESP32_FlushNoLock(CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#else
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esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH,
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APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#endif
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#endif
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while (1) {
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if (esp_cpu_in_ocd_debug_mode()) {
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__asm__ ("break 0,0");
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}
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*((int *) 0) = 0;
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}
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}
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void abort(void)
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{
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#if !CONFIG_ESP32S2_PANIC_SILENT_REBOOT
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ets_printf("abort() was called at PC 0x%08x on core %d\r\n", (intptr_t)__builtin_return_address(0) - 3, xPortGetCoreID());
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#endif
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/* Calling code might have set other reset reason hint (such as Task WDT),
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* don't overwrite that.
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*/
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if (esp_reset_reason_get_hint() == ESP_RST_UNKNOWN) {
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esp_reset_reason_set_hint(ESP_RST_PANIC);
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}
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invoke_abort();
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}
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static const char *edesc[] = {
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"IllegalInstruction", "Syscall", "InstructionFetchError", "LoadStoreError",
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"Level1Interrupt", "Alloca", "IntegerDivideByZero", "PCValue",
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"Privileged", "LoadStoreAlignment", "res", "res",
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"InstrPDAddrError", "LoadStorePIFDataError", "InstrPIFAddrError", "LoadStorePIFAddrError",
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"InstTLBMiss", "InstTLBMultiHit", "InstFetchPrivilege", "res",
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"InstrFetchProhibited", "res", "res", "res",
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"LoadStoreTLBMiss", "LoadStoreTLBMultihit", "LoadStorePrivilege", "res",
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"LoadProhibited", "StoreProhibited", "res", "res",
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"Cp0Dis", "Cp1Dis", "Cp2Dis", "Cp3Dis",
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"Cp4Dis", "Cp5Dis", "Cp6Dis", "Cp7Dis"
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};
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#define NUM_EDESCS (sizeof(edesc) / sizeof(char *))
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static void commonErrorHandler(XtExcFrame *frame);
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static inline void disableAllWdts(void);
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//The fact that we've panic'ed probably means the other CPU is now running wild, possibly
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//messing up the serial output, so we stall it here.
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static void haltOtherCore(void)
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{
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esp_cpu_stall( xPortGetCoreID() == 0 ? 1 : 0 );
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}
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static void setFirstBreakpoint(uint32_t pc)
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{
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asm(
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"wsr.ibreaka0 %0\n" \
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"rsr.ibreakenable a3\n" \
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"movi a4,1\n" \
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"or a4, a4, a3\n" \
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"wsr.ibreakenable a4\n" \
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::"r"(pc):"a3", "a4");
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}
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static inline void printCacheError(void)
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{
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uint32_t vaddr = 0, size = 0;
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uint32_t status[2];
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status[0] = REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG);
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status[1] = REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG);
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for (int i = 0; i < 32; i++) {
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switch (status[0] & BIT(i)) {
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case EXTMEM_IC_SYNC_SIZE_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC0_REG);
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size = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC1_REG);
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panicPutStr("Icache sync parameter configuration error, the error address and size is 0x");
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panicPutHex(vaddr);
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panicPutStr("(0x");
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panicPutHex(size);
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panicPutStr(")\r\n");
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break;
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case EXTMEM_IC_PRELOAD_SIZE_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG);
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size = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG);
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panicPutStr("Icache preload parameter configuration error, the error address and size is 0x");
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panicPutHex(vaddr);
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panicPutStr("(0x");
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panicPutHex(size);
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panicPutStr(")\r\n");
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break;
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case EXTMEM_ICACHE_REJECT_ST:
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vaddr = REG_READ(EXTMEM_PRO_ICACHE_REJECT_VADDR_REG);
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panicPutStr("Icache reject error occurred while accessing the address 0x");
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panicPutHex(vaddr);
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if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
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panicPutStr(" (invalid mmu entry)");
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}
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panicPutStr("\r\n");
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break;
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default:
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break;
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}
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switch (status[1] & BIT(i)) {
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case EXTMEM_DC_SYNC_SIZE_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC0_REG);
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size = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC1_REG);
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panicPutStr("Dcache sync parameter configuration error, the error address and size is 0x");
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panicPutHex(vaddr);
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panicPutStr("(0x");
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panicPutHex(size);
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panicPutStr(")\r\n");
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break;
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case EXTMEM_DC_PRELOAD_SIZE_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG);
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size = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG);
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panicPutStr("Dcache preload parameter configuration error, the error address and size is 0x");
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panicPutHex(vaddr);
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panicPutStr("(0x");
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panicPutHex(size);
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panicPutStr(")\r\n");
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break;
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case EXTMEM_DCACHE_WRITE_FLASH_ST:
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panicPutStr("Write back error occurred while dcache tries to write back to flash\r\n");
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break;
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case EXTMEM_DCACHE_REJECT_ST:
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vaddr = REG_READ(EXTMEM_PRO_DCACHE_REJECT_VADDR_REG);
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panicPutStr("Dcache reject error occurred while accessing the address 0x");
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panicPutHex(vaddr);
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if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
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panicPutStr(" (invalid mmu entry)");
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}
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panicPutStr("\r\n");
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break;
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case EXTMEM_MMU_ENTRY_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_REG);
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panicPutStr("MMU entry fault error occurred while accessing the address 0x");
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panicPutHex(vaddr);
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if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
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panicPutStr(" (invalid mmu entry)");
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}
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panicPutStr("\r\n");
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break;
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default:
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break;
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}
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}
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panicPutStr("\r\n");
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}
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void panicHandler(XtExcFrame *frame)
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{
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int core_id = xPortGetCoreID();
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//Please keep in sync with PANIC_RSN_* defines
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const char *reasons[] = {
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"Unknown reason",
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"Unhandled debug exception",
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"Double exception",
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"Unhandled kernel exception",
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"Coprocessor exception",
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"Interrupt wdt timeout on CPU0",
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"Interrupt wdt timeout on CPU1",
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"Cache exception",
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};
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const char *reason = reasons[0];
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//The panic reason is stored in the EXCCAUSE register.
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if (frame->exccause <= PANIC_RSN_MAX) {
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reason = reasons[frame->exccause];
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}
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if (frame->exccause == PANIC_RSN_INTWDT_CPU0) {
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esp_reset_reason_set_hint(ESP_RST_INT_WDT);
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}
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haltOtherCore();
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panicPutStr("Guru Meditation Error: Core ");
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panicPutDec(core_id);
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panicPutStr(" panic'ed (");
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panicPutStr(reason);
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panicPutStr(")\r\n");
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if (frame->exccause == PANIC_RSN_DEBUGEXCEPTION) {
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int debugRsn;
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asm("rsr.debugcause %0":"=r"(debugRsn));
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panicPutStr("Debug exception reason: ");
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if (debugRsn & XCHAL_DEBUGCAUSE_ICOUNT_MASK) {
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panicPutStr("SingleStep ");
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}
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if (debugRsn & XCHAL_DEBUGCAUSE_IBREAK_MASK) {
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panicPutStr("HwBreakpoint ");
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}
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if (debugRsn & XCHAL_DEBUGCAUSE_DBREAK_MASK) {
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//Unlike what the ISA manual says, this core seemingly distinguishes from a DBREAK
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//reason caused by watchdog 0 and one caused by watchdog 1 by setting bit 8 of the
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//debugcause if the cause is watchdog 1 and clearing it if it's watchdog 0.
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if (debugRsn & (1 << 8)) {
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#if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK
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const char *name = pcTaskGetTaskName(xTaskGetCurrentTaskHandleForCPU(core_id));
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panicPutStr("Stack canary watchpoint triggered (");
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panicPutStr(name);
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panicPutStr(") ");
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#else
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panicPutStr("Watchpoint 1 triggered ");
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#endif
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} else {
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panicPutStr("Watchpoint 0 triggered ");
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}
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}
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if (debugRsn & XCHAL_DEBUGCAUSE_BREAK_MASK) {
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panicPutStr("BREAK instr ");
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}
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if (debugRsn & XCHAL_DEBUGCAUSE_BREAKN_MASK) {
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panicPutStr("BREAKN instr ");
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}
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if (debugRsn & XCHAL_DEBUGCAUSE_DEBUGINT_MASK) {
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panicPutStr("DebugIntr ");
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}
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panicPutStr("\r\n");
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} else if (frame->exccause == PANIC_RSN_CACHEERR) {
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panicPutStr(" ^~~~~~~~~~~~~~~\r\n");
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printCacheError();
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}
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if (esp_cpu_in_ocd_debug_mode()) {
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disableAllWdts();
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if (frame->exccause == PANIC_RSN_INTWDT_CPU0 ||
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frame->exccause == PANIC_RSN_INTWDT_CPU1) {
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TIMERG1.int_clr.wdt = 1;
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}
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#if CONFIG_APPTRACE_ENABLE
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#if CONFIG_SYSVIEW_ENABLE
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SEGGER_RTT_ESP32_FlushNoLock(CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#else
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esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH,
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APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#endif
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#endif
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setFirstBreakpoint(frame->pc);
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return;
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}
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commonErrorHandler(frame);
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}
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void xt_unhandled_exception(XtExcFrame *frame)
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{
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haltOtherCore();
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if (!abort_called) {
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panicPutStr("Guru Meditation Error: Core ");
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panicPutDec(xPortGetCoreID());
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panicPutStr(" panic'ed (");
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int exccause = frame->exccause;
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if (exccause < NUM_EDESCS) {
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panicPutStr(edesc[exccause]);
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} else {
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panicPutStr("Unknown");
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}
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panicPutStr(")");
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if (esp_cpu_in_ocd_debug_mode()) {
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panicPutStr(" at pc=");
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panicPutHex(frame->pc);
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panicPutStr(". Setting bp and returning..\r\n");
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#if CONFIG_APPTRACE_ENABLE
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#if CONFIG_SYSVIEW_ENABLE
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SEGGER_RTT_ESP32_FlushNoLock(CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#else
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esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH,
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APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#endif
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#endif
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//Stick a hardware breakpoint on the address the handler returns to. This way, the OCD debugger
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//will kick in exactly at the context the error happened.
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setFirstBreakpoint(frame->pc);
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return;
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}
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panicPutStr(". Exception was unhandled.\r\n");
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esp_reset_reason_set_hint(ESP_RST_PANIC);
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}
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commonErrorHandler(frame);
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}
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/*
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If watchdogs are enabled, the panic handler runs the risk of getting aborted pre-emptively because
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an overzealous watchdog decides to reset it. On the other hand, if we disable all watchdogs, we run
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the risk of somehow halting in the panic handler and not resetting. That is why this routine kills
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all watchdogs except the timer group 0 watchdog, and it reconfigures that to reset the chip after
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one second.
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*/
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static void reconfigureAllWdts(void)
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{
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TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
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TIMERG0.wdt_feed = 1;
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TIMERG0.wdt_config0.sys_reset_length = 7; //3.2uS
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TIMERG0.wdt_config0.cpu_reset_length = 7; //3.2uS
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TIMERG0.wdt_config0.stg0 = TIMG_WDT_STG_SEL_RESET_SYSTEM; //1st stage timeout: reset system
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TIMERG0.wdt_config1.clk_prescale = 80 * 500; //Prescaler: wdt counts in ticks of 0.5mS
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TIMERG0.wdt_config2 = 2000; //1 second before reset
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TIMERG0.wdt_config0.en = 1;
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TIMERG0.wdt_wprotect = 0;
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//Disable wdt 1
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TIMERG1.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
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TIMERG1.wdt_config0.en = 0;
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TIMERG1.wdt_wprotect = 0;
|
|
}
|
|
|
|
/*
|
|
This disables all the watchdogs for when we call the gdbstub.
|
|
*/
|
|
static inline void disableAllWdts(void)
|
|
{
|
|
TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
|
|
TIMERG0.wdt_config0.en = 0;
|
|
TIMERG0.wdt_wprotect = 0;
|
|
TIMERG1.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
|
|
TIMERG1.wdt_config0.en = 0;
|
|
TIMERG1.wdt_wprotect = 0;
|
|
}
|
|
|
|
#if CONFIG_ESP32S2_PANIC_PRINT_REBOOT || CONFIG_ESP32S2_PANIC_SILENT_REBOOT
|
|
|
|
static void esp_panic_dig_reset(void) __attribute__((noreturn));
|
|
|
|
static void esp_panic_dig_reset(void)
|
|
{
|
|
// make sure all the panic handler output is sent from UART FIFO
|
|
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
|
|
// switch to XTAL (otherwise we will keep running from the PLL)
|
|
rtc_clk_cpu_freq_set_xtal();
|
|
// reset the digital part
|
|
esp_cpu_unstall(PRO_CPU_NUM);
|
|
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
|
|
while (true) {
|
|
;
|
|
}
|
|
}
|
|
|
|
#endif
|
|
|
|
static void putEntry(uint32_t pc, uint32_t sp)
|
|
{
|
|
if (pc & 0x80000000) {
|
|
pc = (pc & 0x3fffffff) | 0x40000000;
|
|
}
|
|
panicPutStr(" 0x");
|
|
panicPutHex(pc);
|
|
panicPutStr(":0x");
|
|
panicPutHex(sp);
|
|
}
|
|
|
|
static void doBacktrace(XtExcFrame *frame)
|
|
{
|
|
uint32_t i = 0, pc = frame->pc, sp = frame->a1;
|
|
panicPutStr("\r\nBacktrace:");
|
|
/* Do not check sanity on first entry, PC could be smashed. */
|
|
putEntry(pc, sp);
|
|
pc = frame->a0;
|
|
while (i++ < 100) {
|
|
uint32_t psp = sp;
|
|
if (!esp_stack_ptr_is_sane(sp) || i++ > 100) {
|
|
break;
|
|
}
|
|
sp = *((uint32_t *) (sp - 0x10 + 4));
|
|
putEntry(pc - 3, sp); // stack frame addresses are return addresses, so subtract 3 to get the CALL address
|
|
pc = *((uint32_t *) (psp - 0x10));
|
|
if (pc < 0x40000000) {
|
|
break;
|
|
}
|
|
}
|
|
panicPutStr("\r\n\r\n");
|
|
}
|
|
|
|
/*
|
|
* Dump registers and do backtrace.
|
|
*/
|
|
static void commonErrorHandler_dump(XtExcFrame *frame, int core_id)
|
|
{
|
|
int *regs = (int *)frame;
|
|
int x, y;
|
|
const char *sdesc[] = {
|
|
"PC ", "PS ", "A0 ", "A1 ", "A2 ", "A3 ", "A4 ", "A5 ",
|
|
"A6 ", "A7 ", "A8 ", "A9 ", "A10 ", "A11 ", "A12 ", "A13 ",
|
|
"A14 ", "A15 ", "SAR ", "EXCCAUSE", "EXCVADDR", "LBEG ", "LEND ", "LCOUNT "
|
|
};
|
|
|
|
/* only dump registers for 'real' crashes, if crashing via abort()
|
|
the register window is no longer useful.
|
|
*/
|
|
if (!abort_called) {
|
|
panicPutStr("Core");
|
|
panicPutDec(core_id);
|
|
panicPutStr(" register dump:\r\n");
|
|
|
|
for (x = 0; x < 24; x += 4) {
|
|
for (y = 0; y < 4; y++) {
|
|
if (sdesc[x + y][0] != 0) {
|
|
panicPutStr(sdesc[x + y]);
|
|
panicPutStr(": 0x");
|
|
panicPutHex(regs[x + y + 1]);
|
|
panicPutStr(" ");
|
|
}
|
|
}
|
|
panicPutStr("\r\n");
|
|
}
|
|
|
|
if (xPortInterruptedFromISRContext()) {
|
|
//If the core which triggers the interrupt watchdog was in ISR context, dump the epc registers.
|
|
uint32_t __value;
|
|
panicPutStr("Core");
|
|
panicPutDec(core_id);
|
|
panicPutStr(" was running in ISR context:\r\n");
|
|
|
|
__asm__("rsr.epc1 %0" : "=a"(__value));
|
|
panicPutStr("EPC1 : 0x");
|
|
panicPutHex(__value);
|
|
|
|
__asm__("rsr.epc2 %0" : "=a"(__value));
|
|
panicPutStr(" EPC2 : 0x");
|
|
panicPutHex(__value);
|
|
|
|
__asm__("rsr.epc3 %0" : "=a"(__value));
|
|
panicPutStr(" EPC3 : 0x");
|
|
panicPutHex(__value);
|
|
|
|
__asm__("rsr.epc4 %0" : "=a"(__value));
|
|
panicPutStr(" EPC4 : 0x");
|
|
panicPutHex(__value);
|
|
|
|
panicPutStr("\r\n");
|
|
}
|
|
|
|
}
|
|
|
|
/* With windowed ABI backtracing is easy, let's do it. */
|
|
doBacktrace(frame);
|
|
|
|
}
|
|
|
|
/*
|
|
We arrive here after a panic or unhandled exception, when no OCD is detected. Dump the registers to the
|
|
serial port and either jump to the gdb stub, halt the CPU or reboot.
|
|
*/
|
|
static __attribute__((noreturn)) void commonErrorHandler(XtExcFrame *frame)
|
|
{
|
|
|
|
int core_id = xPortGetCoreID();
|
|
// start panic WDT to restart system if we hang in this handler
|
|
if (!rtc_wdt_is_on()) {
|
|
rtc_wdt_protect_off();
|
|
rtc_wdt_disable();
|
|
rtc_wdt_set_length_of_reset_signal(RTC_WDT_SYS_RESET_SIG, RTC_WDT_LENGTH_3_2us);
|
|
rtc_wdt_set_length_of_reset_signal(RTC_WDT_CPU_RESET_SIG, RTC_WDT_LENGTH_3_2us);
|
|
rtc_wdt_set_stage(RTC_WDT_STAGE0, RTC_WDT_STAGE_ACTION_RESET_SYSTEM);
|
|
// 64KB of core dump data (stacks of about 30 tasks) will produce ~85KB base64 data.
|
|
// @ 115200 UART speed it will take more than 6 sec to print them out.
|
|
rtc_wdt_set_time(RTC_WDT_STAGE0, 7000);
|
|
rtc_wdt_enable();
|
|
rtc_wdt_protect_on();
|
|
}
|
|
|
|
//Feed the watchdogs, so they will give us time to print out debug info
|
|
reconfigureAllWdts();
|
|
|
|
commonErrorHandler_dump(frame, core_id);
|
|
|
|
#if CONFIG_APPTRACE_ENABLE
|
|
disableAllWdts();
|
|
#if CONFIG_SYSVIEW_ENABLE
|
|
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
|
|
#else
|
|
esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH,
|
|
APPTRACE_ONPANIC_HOST_FLUSH_TMO);
|
|
#endif
|
|
reconfigureAllWdts();
|
|
#endif
|
|
|
|
#if CONFIG_ESP32S2_PANIC_GDBSTUB
|
|
disableAllWdts();
|
|
rtc_wdt_disable();
|
|
panicPutStr("Entering gdb stub now.\r\n");
|
|
esp_gdbstub_panic_handler(frame);
|
|
#else
|
|
#if CONFIG_ESP32_ENABLE_COREDUMP
|
|
static bool s_dumping_core;
|
|
if (s_dumping_core) {
|
|
panicPutStr("Re-entered core dump! Exception happened during core dump!\r\n");
|
|
} else {
|
|
disableAllWdts();
|
|
s_dumping_core = true;
|
|
#if CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH
|
|
esp_core_dump_to_flash(frame);
|
|
#endif
|
|
#if CONFIG_ESP32_ENABLE_COREDUMP_TO_UART && !CONFIG_ESP32S2_PANIC_SILENT_REBOOT
|
|
esp_core_dump_to_uart(frame);
|
|
#endif
|
|
s_dumping_core = false;
|
|
reconfigureAllWdts();
|
|
}
|
|
#endif /* CONFIG_ESP32_ENABLE_COREDUMP */
|
|
rtc_wdt_disable();
|
|
#if CONFIG_ESP32S2_PANIC_PRINT_REBOOT || CONFIG_ESP32S2_PANIC_SILENT_REBOOT
|
|
panicPutStr("Rebooting...\r\n");
|
|
if (frame->exccause != PANIC_RSN_CACHEERR) {
|
|
esp_restart_noos();
|
|
} else {
|
|
// The only way to clear invalid cache access interrupt is to reset the digital part
|
|
esp_panic_dig_reset();
|
|
}
|
|
#else
|
|
disableAllWdts();
|
|
panicPutStr("CPU halted.\r\n");
|
|
while (1);
|
|
#endif /* CONFIG_ESP32S2_PANIC_PRINT_REBOOT || CONFIG_ESP32S2_PANIC_SILENT_REBOOT */
|
|
#endif /* CONFIG_ESP32S2_PANIC_GDBSTUB */
|
|
}
|
|
|
|
|
|
void esp_set_breakpoint_if_jtag(void *fn)
|
|
{
|
|
if (esp_cpu_in_ocd_debug_mode()) {
|
|
setFirstBreakpoint((uint32_t)fn);
|
|
}
|
|
}
|
|
|
|
void _esp_error_check_failed(esp_err_t rc, const char *file, int line, const char *function, const char *expression)
|
|
{
|
|
ets_printf("ESP_ERROR_CHECK failed: esp_err_t 0x%x", rc);
|
|
#ifdef CONFIG_ESP_ERR_TO_NAME_LOOKUP
|
|
ets_printf(" (%s)", esp_err_to_name(rc));
|
|
#endif //CONFIG_ESP_ERR_TO_NAME_LOOKUP
|
|
ets_printf(" at 0x%08x\n", (intptr_t)__builtin_return_address(0) - 3);
|
|
if (spi_flash_cache_enabled()) { // strings may be in flash cache
|
|
ets_printf("file: \"%s\" line %d\nfunc: %s\nexpression: %s\n", file, line, function, expression);
|
|
}
|
|
invoke_abort();
|
|
}
|