OVMS3-idf/examples/ethernet/iperf/main/Kconfig.projbuild
suda-morris ae2cec834e ethernet: add kconfig help for GPIO0 output mode
1. add kconfig help for GPIO0 output mode
2. fix a bug when select gpio0 output mode and initialize psram
3. make default config to official development board
4. fix wrong LAN8720 register index
2019-10-14 10:50:49 +08:00

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menu "Example Configuration"
config STORE_HISTORY
bool "Store command history in flash"
default y
help
Linenoise line editing library provides functions to save and load
command history. If this option is enabled, initalizes a FAT filesystem
and uses it to store command history.
menu "Etherent PHY Device"
choice PHY_MODEL
prompt "Ethernet PHY Device"
default PHY_IP101
help
Select the PHY driver to use for the example.
config PHY_IP101
bool "IP101"
help
IP101 is a single port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver.
Goto http://www.icplus.com.tw/pp-IP101G.html for more information about it.
config PHY_TLK110
bool "TLK110"
help
TLK110 is an Industrial 10/100Mbps Ethernet Physical Layer Transceiver.
Goto http://www.ti.com/product/TLK110 for information about it.
config PHY_LAN8720
bool "LAN8720"
help
LAN8720 is a small footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support.
Goto https://www.microchip.com/LAN8720A for more information about it.
endchoice
config PHY_ADDRESS
int "Ethernet PHY Address"
default 1
range 0 31
help
PHY Address of your PHY device. It dependens on your schematic design.
choice PHY_CLOCK_MODE
prompt "Ethernet PHY Clock Mode"
default PHY_CLOCK_GPIO0_IN
help
Select external (input on GPIO0) or internal (output on GPIO0, GPIO16 or GPIO17) RMII clock.
config PHY_CLOCK_GPIO0_IN
bool "GPIO0 Input"
help
Input of 50MHz RMII clock on GPIO0.
config PHY_CLOCK_GPIO0_OUT
bool "GPIO0 Output(READ HELP)"
help
GPIO0 can be set to output a pre-divided PLL clock (test only!).
Enabling this option will configure GPIO0 to output a 50MHz clock.
In fact this clock doesn't have directly relationship with EMAC peripheral.
Sometimes this clock won't work well with your PHY chip. You might need to
add some extra devices after GPIO0 (e.g. inverter).
Note that outputting RMII clock on GPIO0 is an experimental practice.
If you want the Ethernet to work with WiFi, don't select GPIO0 output mode for stability.
config PHY_CLOCK_GPIO16_OUT
bool "GPIO16 Output"
help
Output the internal 50MHz RMII clock on GPIO16.
config PHY_CLOCK_GPIO17_OUT
bool "GPIO17 Output (inverted)"
help
Output the internal 50MHz RMII clock on GPIO17 (inverted signal).
endchoice
config PHY_CLOCK_MODE
int
default 0 if PHY_CLOCK_GPIO0_IN
default 1 if PHY_CLOCK_GPIO0_OUT
default 2 if PHY_CLOCK_GPIO16_OUT
default 3 if PHY_CLOCK_GPIO17_OUT
config PHY_USE_POWER_PIN
bool "Use PHY Power (enable / disable) pin"
default y
help
Use a GPIO "power pin" to power the PHY on/off during operation.
When using GPIO0 to input RMII clock, the reset process will be interfered by this clock.
So we need another GPIO to control the switch on / off of the RMII clock.
if PHY_USE_POWER_PIN
config PHY_POWER_PIN
int "PHY Power GPIO"
default 5
range 0 33
depends on PHY_USE_POWER_PIN
help
GPIO number to use for powering on/off the PHY.
endif
endmenu
menu "Etherent SMI interface"
config PHY_SMI_MDC_PIN
int "SMI MDC Pin Number"
default 23
range 0 33
help
GPIO number used for SMI clock signal.
config PHY_SMI_MDIO_PIN
int "SMI MDIO Pin Number"
default 18
range 0 33
help
GPIO number used for SMI data signal.
endmenu
endmenu