8bba348528
This commit resolves a blocking in esp_aes_block function. Introduce: The problem was in the fact that AES is switched off at the moment when he should give out the processed data. But because of the disabled, the operation can not be completed successfully, there is an infinite hang. The reason for this behavior is that the registers for controlling the inclusion of AES, SHA, MPI have shared registers and they were not protected from sharing. Fix some related issue with shared using of AES SHA RSA accelerators. Closes: https://github.com/espressif/esp-idf/issues/2295#issuecomment-432898137
260 lines
9.2 KiB
C
260 lines
9.2 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <esp_types.h>
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#include "esp_intr.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/xtensa_api.h"
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#include "soc/dport_reg.h"
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#include "driver/periph_ctrl.h"
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static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
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/* Static functions to return register address & mask for clk_en / rst of each peripheral */
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static uint32_t get_clk_en_mask(periph_module_t periph);
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static uint32_t get_rst_en_mask(periph_module_t periph, bool enable);
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static uint32_t get_clk_en_reg(periph_module_t periph);
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static uint32_t get_rst_en_reg(periph_module_t periph);
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void periph_module_enable(periph_module_t periph)
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{
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portENTER_CRITICAL(&periph_spinlock);
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DPORT_SET_PERI_REG_MASK(get_clk_en_reg(periph), get_clk_en_mask(periph));
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DPORT_CLEAR_PERI_REG_MASK(get_rst_en_reg(periph), get_rst_en_mask(periph, true));
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portEXIT_CRITICAL(&periph_spinlock);
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}
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void periph_module_disable(periph_module_t periph)
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{
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portENTER_CRITICAL(&periph_spinlock);
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DPORT_CLEAR_PERI_REG_MASK(get_clk_en_reg(periph), get_clk_en_mask(periph));
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DPORT_SET_PERI_REG_MASK(get_rst_en_reg(periph), get_rst_en_mask(periph, false));
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portEXIT_CRITICAL(&periph_spinlock);
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}
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void periph_module_reset(periph_module_t periph)
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{
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portENTER_CRITICAL(&periph_spinlock);
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DPORT_SET_PERI_REG_MASK(get_rst_en_reg(periph), get_rst_en_mask(periph, false));
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DPORT_CLEAR_PERI_REG_MASK(get_rst_en_reg(periph), get_rst_en_mask(periph, false));
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portEXIT_CRITICAL(&periph_spinlock);
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}
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static uint32_t get_clk_en_mask(periph_module_t periph)
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{
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switch(periph) {
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case PERIPH_RMT_MODULE:
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return DPORT_RMT_CLK_EN;
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case PERIPH_LEDC_MODULE:
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return DPORT_LEDC_CLK_EN;
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case PERIPH_UART0_MODULE:
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return DPORT_UART_CLK_EN;
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case PERIPH_UART1_MODULE:
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return DPORT_UART1_CLK_EN;
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case PERIPH_UART2_MODULE:
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return DPORT_UART2_CLK_EN;
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case PERIPH_I2C0_MODULE:
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return DPORT_I2C_EXT0_CLK_EN;
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case PERIPH_I2C1_MODULE:
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return DPORT_I2C_EXT1_CLK_EN;
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case PERIPH_I2S0_MODULE:
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return DPORT_I2S0_CLK_EN;
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case PERIPH_I2S1_MODULE:
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return DPORT_I2S1_CLK_EN;
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case PERIPH_TIMG0_MODULE:
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return DPORT_TIMERGROUP_CLK_EN;
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case PERIPH_TIMG1_MODULE:
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return DPORT_TIMERGROUP1_CLK_EN;
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case PERIPH_PWM0_MODULE:
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return DPORT_PWM0_CLK_EN;
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case PERIPH_PWM1_MODULE:
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return DPORT_PWM1_CLK_EN;
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case PERIPH_PWM2_MODULE:
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return DPORT_PWM2_CLK_EN;
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case PERIPH_PWM3_MODULE:
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return DPORT_PWM3_CLK_EN;
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case PERIPH_UHCI0_MODULE:
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return DPORT_UHCI0_CLK_EN;
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case PERIPH_UHCI1_MODULE:
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return DPORT_UHCI1_CLK_EN;
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case PERIPH_PCNT_MODULE:
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return DPORT_PCNT_CLK_EN;
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case PERIPH_SPI_MODULE:
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return DPORT_SPI01_CLK_EN;
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case PERIPH_HSPI_MODULE:
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return DPORT_SPI2_CLK_EN;
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case PERIPH_VSPI_MODULE:
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return DPORT_SPI3_CLK_EN;
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case PERIPH_SPI_DMA_MODULE:
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return DPORT_SPI_DMA_CLK_EN;
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case PERIPH_SDMMC_MODULE:
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return DPORT_WIFI_CLK_SDIO_HOST_EN;
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case PERIPH_SDIO_SLAVE_MODULE:
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return DPORT_WIFI_CLK_SDIOSLAVE_EN;
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case PERIPH_CAN_MODULE:
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return DPORT_CAN_CLK_EN;
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case PERIPH_EMAC_MODULE:
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return DPORT_WIFI_CLK_EMAC_EN;
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case PERIPH_RNG_MODULE:
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return DPORT_WIFI_CLK_RNG_EN;
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case PERIPH_WIFI_MODULE:
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return DPORT_WIFI_CLK_WIFI_EN_M;
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case PERIPH_BT_MODULE:
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return DPORT_WIFI_CLK_BT_EN_M;
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case PERIPH_WIFI_BT_COMMON_MODULE:
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return DPORT_WIFI_CLK_WIFI_BT_COMMON_M;
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case PERIPH_BT_BASEBAND_MODULE:
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return DPORT_BT_BASEBAND_EN;
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case PERIPH_BT_LC_MODULE:
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return DPORT_BT_LC_EN;
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case PERIPH_AES_MODULE:
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return DPORT_PERI_EN_AES;
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case PERIPH_SHA_MODULE:
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return DPORT_PERI_EN_SHA;
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case PERIPH_RSA_MODULE:
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return DPORT_PERI_EN_RSA;
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default:
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return 0;
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}
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}
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static uint32_t get_rst_en_mask(periph_module_t periph, bool enable)
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{
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switch(periph) {
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case PERIPH_RMT_MODULE:
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return DPORT_RMT_RST;
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case PERIPH_LEDC_MODULE:
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return DPORT_LEDC_RST;
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case PERIPH_UART0_MODULE:
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return DPORT_UART_RST;
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case PERIPH_UART1_MODULE:
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return DPORT_UART1_RST;
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case PERIPH_UART2_MODULE:
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return DPORT_UART2_RST;
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case PERIPH_I2C0_MODULE:
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return DPORT_I2C_EXT0_RST;
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case PERIPH_I2C1_MODULE:
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return DPORT_I2C_EXT1_RST;
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case PERIPH_I2S0_MODULE:
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return DPORT_I2S0_RST;
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case PERIPH_I2S1_MODULE:
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return DPORT_I2S1_RST;
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case PERIPH_TIMG0_MODULE:
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return DPORT_TIMERGROUP_RST;
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case PERIPH_TIMG1_MODULE:
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return DPORT_TIMERGROUP1_RST;
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case PERIPH_PWM0_MODULE:
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return DPORT_PWM0_RST;
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case PERIPH_PWM1_MODULE:
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return DPORT_PWM1_RST;
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case PERIPH_PWM2_MODULE:
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return DPORT_PWM2_RST;
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case PERIPH_PWM3_MODULE:
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return DPORT_PWM3_RST;
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case PERIPH_UHCI0_MODULE:
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return DPORT_UHCI0_RST;
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case PERIPH_UHCI1_MODULE:
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return DPORT_UHCI1_RST;
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case PERIPH_PCNT_MODULE:
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return DPORT_PCNT_RST;
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case PERIPH_SPI_MODULE:
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return DPORT_SPI01_RST;
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case PERIPH_HSPI_MODULE:
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return DPORT_SPI2_RST;
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case PERIPH_VSPI_MODULE:
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return DPORT_SPI3_RST;
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case PERIPH_SPI_DMA_MODULE:
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return DPORT_SPI_DMA_RST;
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case PERIPH_SDMMC_MODULE:
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return DPORT_SDIO_HOST_RST;
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case PERIPH_SDIO_SLAVE_MODULE:
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return DPORT_SDIO_RST;
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case PERIPH_CAN_MODULE:
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return DPORT_CAN_RST;
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case PERIPH_EMAC_MODULE:
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return DPORT_EMAC_RST;
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case PERIPH_AES_MODULE:
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if (enable == true) {
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// Clear reset on digital signature & secure boot units, otherwise AES unit is held in reset also.
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return (DPORT_PERI_EN_AES | DPORT_PERI_EN_DIGITAL_SIGNATURE | DPORT_PERI_EN_SECUREBOOT);
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} else {
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//Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively.
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return DPORT_PERI_EN_AES;
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}
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case PERIPH_SHA_MODULE:
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if (enable == true) {
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// Clear reset on secure boot, otherwise SHA is held in reset
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return (DPORT_PERI_EN_SHA | DPORT_PERI_EN_SECUREBOOT);
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} else {
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// Don't assert reset on secure boot, otherwise AES is held in reset
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return DPORT_PERI_EN_SHA;
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}
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case PERIPH_RSA_MODULE:
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if (enable == true) {
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// Also clear reset on digital signature, otherwise RSA is held in reset
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return (DPORT_PERI_EN_RSA | DPORT_PERI_EN_DIGITAL_SIGNATURE);
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} else {
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// Don't reset digital signature unit, as this resets AES also
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return DPORT_PERI_EN_RSA;
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}
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case PERIPH_WIFI_MODULE:
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case PERIPH_BT_MODULE:
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case PERIPH_WIFI_BT_COMMON_MODULE:
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case PERIPH_BT_BASEBAND_MODULE:
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case PERIPH_BT_LC_MODULE:
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return 0;
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default:
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return 0;
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}
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}
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static bool is_wifi_clk_peripheral(periph_module_t periph)
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{
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/* A small subset of peripherals use WIFI_CLK_EN_REG and
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CORE_RST_EN_REG for their clock & reset registers */
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switch(periph) {
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case PERIPH_SDMMC_MODULE:
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case PERIPH_SDIO_SLAVE_MODULE:
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case PERIPH_EMAC_MODULE:
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case PERIPH_RNG_MODULE:
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case PERIPH_WIFI_MODULE:
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case PERIPH_BT_MODULE:
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case PERIPH_WIFI_BT_COMMON_MODULE:
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case PERIPH_BT_BASEBAND_MODULE:
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case PERIPH_BT_LC_MODULE:
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return true;
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default:
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return false;
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}
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}
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static uint32_t get_clk_en_reg(periph_module_t periph)
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{
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if (periph == PERIPH_AES_MODULE || periph == PERIPH_SHA_MODULE || periph == PERIPH_RSA_MODULE) {
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return DPORT_PERI_CLK_EN_REG;
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} else {
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return is_wifi_clk_peripheral(periph) ? DPORT_WIFI_CLK_EN_REG : DPORT_PERIP_CLK_EN_REG;
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}
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}
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static uint32_t get_rst_en_reg(periph_module_t periph)
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{
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if (periph == PERIPH_AES_MODULE || periph == PERIPH_SHA_MODULE || periph == PERIPH_RSA_MODULE) {
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return DPORT_PERI_RST_EN_REG;
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} else {
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return is_wifi_clk_peripheral(periph) ? DPORT_CORE_RST_EN_REG : DPORT_PERIP_RST_EN_REG;
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}
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}
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