15 lines
916 B
Plaintext
15 lines
916 B
Plaintext
/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
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/* The load addresses are defined later using the AT statements. */
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x18000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
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dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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}
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_heap_end = 0x3fffe000;
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