2b7681ec4f
There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
95 lines
3.3 KiB
C
95 lines
3.3 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include "spi_flash_chip_generic.h"
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#include "spi_flash_defs.h"
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/* Driver for ISSI flash chip, as used in ESP32 D2WD */
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esp_err_t spi_flash_chip_issi_probe(esp_flash_t *chip, uint32_t flash_id)
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{
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/* Check manufacturer and product IDs match our desired masks */
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const uint8_t MFG_ID = 0x9D;
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if (flash_id >> 16 != MFG_ID) {
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return ESP_ERR_NOT_FOUND;
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}
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const uint16_t FLASH_ID_MASK = 0xCF00;
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const uint16_t FLASH_ID_VALUE = 0x4000;
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if ((flash_id & FLASH_ID_MASK) != FLASH_ID_VALUE) {
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return ESP_ERR_NOT_FOUND;
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}
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return ESP_OK;
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}
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esp_err_t spi_flash_chip_issi_set_io_mode(esp_flash_t *chip)
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{
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/* ISSI uses bit 6 of "basic" SR as Quad Enable */
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const uint8_t BIT_QE = 1 << 6;
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return spi_flash_common_set_io_mode(chip,
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spi_flash_common_write_status_8b_wrsr,
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spi_flash_common_read_status_8b_rdsr,
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BIT_QE);
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}
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esp_err_t spi_flash_chip_issi_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
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{
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/* ISSI uses bit 6 of "basic" SR as Quad Enable */
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const uint8_t BIT_QE = 1 << 6;
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uint32_t sr;
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esp_err_t ret = spi_flash_common_read_status_8b_rdsr(chip, &sr);
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if (ret == ESP_OK) {
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*out_io_mode = ((sr & BIT_QE)? SPI_FLASH_QOUT: 0);
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}
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return ret;
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}
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static const char chip_name[] = "issi";
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// The issi chip can use the functions for generic chips except from set read mode and probe,
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// So we only replace these two functions.
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const spi_flash_chip_t esp_flash_chip_issi = {
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.name = chip_name,
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.probe = spi_flash_chip_issi_probe,
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.reset = spi_flash_chip_generic_reset,
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.detect_size = spi_flash_chip_generic_detect_size,
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.erase_chip = spi_flash_chip_generic_erase_chip,
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.erase_sector = spi_flash_chip_generic_erase_sector,
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.erase_block = spi_flash_chip_generic_erase_block,
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.sector_size = 4 * 1024,
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.block_erase_size = 64 * 1024,
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.get_chip_write_protect = spi_flash_chip_generic_get_write_protect,
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.set_chip_write_protect = spi_flash_chip_generic_set_write_protect,
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// TODO support protected regions on ISSI flash
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.num_protectable_regions = 0,
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.protectable_regions = NULL,
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.get_protected_regions = NULL,
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.set_protected_regions = NULL,
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.read = spi_flash_chip_generic_read,
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.write = spi_flash_chip_generic_write,
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.program_page = spi_flash_chip_generic_page_program,
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.page_size = 256,
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.write_encrypted = spi_flash_chip_generic_write_encrypted,
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.wait_idle = spi_flash_chip_generic_wait_idle,
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.set_io_mode = spi_flash_chip_issi_set_io_mode,
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.get_io_mode = spi_flash_chip_issi_get_io_mode,
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};
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