374 lines
12 KiB
C
374 lines
12 KiB
C
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_UART_STRUCT_H_
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#define _SOC_UART_STRUCT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct {
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union {
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struct {
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uint8_t rw_byte;
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uint8_t reserved[3];
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};
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uint32_t val;
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} ahb_fifo;
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union {
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struct {
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uint32_t rxfifo_full: 1;
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uint32_t txfifo_empty: 1;
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uint32_t parity_err: 1;
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uint32_t frm_err: 1;
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uint32_t rxfifo_ovf: 1;
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uint32_t dsr_chg: 1;
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uint32_t cts_chg: 1;
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uint32_t brk_det: 1;
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uint32_t rxfifo_tout: 1;
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uint32_t sw_xon: 1;
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uint32_t sw_xoff: 1;
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uint32_t glitch_det: 1;
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uint32_t tx_brk_done: 1;
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uint32_t tx_brk_idle_done: 1;
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uint32_t tx_done: 1;
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uint32_t rs485_parity_err: 1;
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uint32_t rs485_frm_err: 1;
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uint32_t rs485_clash: 1;
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uint32_t at_cmd_char_det: 1;
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uint32_t wakeup: 1;
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t rxfifo_full: 1;
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uint32_t txfifo_empty: 1;
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uint32_t parity_err: 1;
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uint32_t frm_err: 1;
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uint32_t rxfifo_ovf: 1;
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uint32_t dsr_chg: 1;
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uint32_t cts_chg: 1;
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uint32_t brk_det: 1;
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uint32_t rxfifo_tout: 1;
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uint32_t sw_xon: 1;
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uint32_t sw_xoff: 1;
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uint32_t glitch_det: 1;
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uint32_t tx_brk_done: 1;
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uint32_t tx_brk_idle_done: 1;
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uint32_t tx_done: 1;
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uint32_t rs485_parity_err: 1;
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uint32_t rs485_frm_err: 1;
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uint32_t rs485_clash: 1;
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uint32_t at_cmd_char_det: 1;
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uint32_t wakeup: 1;
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t rxfifo_full: 1;
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uint32_t txfifo_empty: 1;
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uint32_t parity_err: 1;
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uint32_t frm_err: 1;
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uint32_t rxfifo_ovf: 1;
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uint32_t dsr_chg: 1;
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uint32_t cts_chg: 1;
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uint32_t brk_det: 1;
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uint32_t rxfifo_tout: 1;
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uint32_t sw_xon: 1;
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uint32_t sw_xoff: 1;
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uint32_t glitch_det: 1;
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uint32_t tx_brk_done: 1;
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uint32_t tx_brk_idle_done: 1;
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uint32_t tx_done: 1;
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uint32_t rs485_parity_err: 1;
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uint32_t rs485_frm_err: 1;
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uint32_t rs485_clash: 1;
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uint32_t at_cmd_char_det: 1;
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uint32_t wakeup: 1;
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t rxfifo_full: 1;
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uint32_t txfifo_empty: 1;
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uint32_t parity_err: 1;
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uint32_t frm_err: 1;
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uint32_t rxfifo_ovf: 1;
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uint32_t dsr_chg: 1;
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uint32_t cts_chg: 1;
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uint32_t brk_det: 1;
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uint32_t rxfifo_tout: 1;
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uint32_t sw_xon: 1;
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uint32_t sw_xoff: 1;
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uint32_t glitch_det: 1;
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uint32_t tx_brk_done: 1;
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uint32_t tx_brk_idle_done: 1;
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uint32_t tx_done: 1;
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uint32_t rs485_parity_err: 1;
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uint32_t rs485_frm_err: 1;
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uint32_t rs485_clash: 1;
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uint32_t at_cmd_char_det: 1;
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uint32_t wakeup: 1;
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t div_int: 20;
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uint32_t div_frag: 4;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} clk_div;
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union {
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struct {
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uint32_t en: 1;
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uint32_t reserved1: 7;
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uint32_t glitch_filt: 8;
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uint32_t reserved16: 16;
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};
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uint32_t val;
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} auto_baud;
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union {
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struct {
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uint32_t rxfifo_cnt:10;
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uint32_t reserved10: 3;
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uint32_t dsrn: 1;
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uint32_t ctsn: 1;
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uint32_t rxd: 1;
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uint32_t txfifo_cnt:10;
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uint32_t reserved26: 3;
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uint32_t dtrn: 1;
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uint32_t rtsn: 1;
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uint32_t txd: 1;
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};
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uint32_t val;
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} status;
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union {
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struct {
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uint32_t parity: 1;
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uint32_t parity_en: 1;
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uint32_t bit_num: 2;
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uint32_t stop_bit_num: 2;
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uint32_t sw_rts: 1;
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uint32_t sw_dtr: 1;
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uint32_t txd_brk: 1;
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uint32_t irda_dplx: 1;
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uint32_t irda_tx_en: 1;
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uint32_t irda_wctl: 1;
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uint32_t irda_tx_inv: 1;
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uint32_t irda_rx_inv: 1;
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uint32_t loopback: 1;
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uint32_t tx_flow_en: 1;
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uint32_t irda_en: 1;
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uint32_t rxfifo_rst: 1;
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uint32_t txfifo_rst: 1;
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uint32_t rxd_inv: 1;
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uint32_t cts_inv: 1;
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uint32_t dsr_inv: 1;
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uint32_t txd_inv: 1;
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uint32_t rts_inv: 1;
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uint32_t dtr_inv: 1;
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uint32_t clk_en: 1;
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uint32_t err_wr_mask: 1;
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uint32_t tick_ref_always_on: 1;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} conf0;
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union {
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struct {
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uint32_t rxfifo_full_thrhd: 9;
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uint32_t txfifo_empty_thrhd: 9;
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uint32_t reserved18: 11;
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uint32_t rx_tout_flow_dis: 1;
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uint32_t rx_flow_en: 1;
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uint32_t rx_tout_en: 1;
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};
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uint32_t val;
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} conf1;
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union {
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struct {
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uint32_t min_cnt: 20;
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} lowpulse;
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union {
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struct {
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uint32_t min_cnt: 20;
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} highpulse;
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union {
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struct {
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uint32_t edge_cnt: 10;
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uint32_t reserved10: 22;
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};
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uint32_t val;
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} rxd_cnt;
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union {
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struct {
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uint32_t sw_flow_con_en: 1;
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uint32_t xonoff_del: 1;
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uint32_t force_xon: 1;
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uint32_t force_xoff: 1;
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uint32_t send_xon: 1;
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uint32_t send_xoff: 1;
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} flow_conf;
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union {
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struct {
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uint32_t active_threshold:10;
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uint32_t reserved10: 22;
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};
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uint32_t val;
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} sleep_conf;
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union {
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struct {
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uint32_t xoff_threshold: 9;
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uint32_t xoff_char: 8;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} swfc_conf0;
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union {
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struct {
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uint32_t xon_threshold: 9;
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uint32_t xon_char: 8;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} swfc_conf1;
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union {
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struct {
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uint32_t rx_idle_thrhd:10;
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uint32_t tx_idle_num: 10;
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uint32_t tx_brk_num: 8;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} idle_conf;
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union {
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struct {
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uint32_t en: 1;
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uint32_t dl0_en: 1;
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uint32_t dl1_en: 1;
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uint32_t tx_rx_en: 1;
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uint32_t rx_busy_tx_en: 1;
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uint32_t rx_dly_num: 1;
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uint32_t tx_dly_num: 4;
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uint32_t reserved10: 22;
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};
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uint32_t val;
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} rs485_conf;
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union {
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struct {
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uint32_t pre_idle_num:16;
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uint32_t reserved16: 16;
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};
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uint32_t val;
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} at_cmd_precnt;
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union {
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struct {
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uint32_t post_idle_num:16;
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uint32_t reserved16: 16;
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};
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uint32_t val;
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} at_cmd_postcnt;
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union {
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struct {
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uint32_t rx_gap_tout:16;
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uint32_t reserved16: 16;
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};
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uint32_t val;
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} at_cmd_gaptout;
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union {
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struct {
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uint32_t data: 8;
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uint32_t char_num: 8;
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uint32_t reserved16: 16;
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};
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uint32_t val;
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} at_cmd_char;
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union {
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struct {
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uint32_t mem_pd: 1;
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uint32_t rx_size: 3;
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uint32_t tx_size: 3;
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uint32_t rx_flow_thrhd: 9;
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uint32_t rx_tout_thrhd:10;
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uint32_t reserved26: 6;
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};
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uint32_t val;
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} mem_conf;
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union {
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struct {
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uint32_t apb_tx_waddr:10;
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uint32_t reserved10: 1;
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uint32_t tx_raddr: 10;
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uint32_t reserved21: 11;
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};
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uint32_t val;
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} mem_tx_status;
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union {
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struct {
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uint32_t apb_rx_raddr:10;
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uint32_t reserved10: 1;
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uint32_t rx_waddr: 10;
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uint32_t reserved21: 11;
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};
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uint32_t val;
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} mem_rx_status;
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union {
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struct {
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uint32_t st_urx_out: 4;
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uint32_t st_utx_out: 4;
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} fsm_status;
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union {
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struct {
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uint32_t min_cnt: 20;
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} pospulse;
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union {
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struct {
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uint32_t min_cnt: 20;
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} negpulse;
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uint32_t date; /**/
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uint32_t id; /**/
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} uart_dev_t;
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extern uart_dev_t UART0;
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extern uart_dev_t UART1;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_UART_STRUCT_H_ */
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