151 lines
4 KiB
C
151 lines
4 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdarg.h>
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#include "esp32/rom/ets_sys.h"
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#include "esp_attr.h"
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#include "esp_spi_flash.h" //for ``g_flash_guard_default_ops``
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#include "esp_flash.h"
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#include "esp_flash_partitions.h"
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/*
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* OS functions providing delay service and arbitration among chips, and with the cache.
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*
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* The cache needs to be disabled when chips on the SPI1 bus is under operation, hence these functions need to be put
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* into the IRAM,and their data should be put into the DRAM.
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*/
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typedef struct {
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int host_id;
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} app_func_arg_t;
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typedef struct {
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int host_id;
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bool no_protect; //to decide whether to check protected region (for the main chip) or not.
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} spi1_app_func_arg_t;
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// in the future we will have arbitration among devices, including flash on the same flash bus
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static IRAM_ATTR esp_err_t spi_bus_acquire(int host_id)
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{
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return ESP_OK;
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}
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static IRAM_ATTR esp_err_t spi_bus_release(int host_id)
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{
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return ESP_OK;
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}
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//for SPI1, we have to disable the cache and interrupts before using the SPI bus
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static IRAM_ATTR esp_err_t spi1_start(void *arg)
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{
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g_flash_guard_default_ops.start();
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spi_bus_acquire(((spi1_app_func_arg_t *)arg)->host_id);
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return ESP_OK;
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}
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static IRAM_ATTR esp_err_t spi1_end(void *arg)
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{
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g_flash_guard_default_ops.end();
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spi_bus_release(((spi1_app_func_arg_t *)arg)->host_id);
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return ESP_OK;
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}
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static esp_err_t spi23_start(void *arg)
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{
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spi_bus_acquire(((app_func_arg_t *)arg)->host_id);
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return ESP_OK;
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}
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static esp_err_t spi23_end(void *arg)
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{
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spi_bus_release(((app_func_arg_t *)arg)->host_id);
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return ESP_OK;
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}
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static IRAM_ATTR esp_err_t delay_us(void *arg, unsigned us)
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{
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ets_delay_us(us);
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return ESP_OK;
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}
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static IRAM_ATTR esp_err_t main_flash_region_protected(void* arg, size_t start_addr, size_t size)
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{
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if (((spi1_app_func_arg_t*)arg)->no_protect || esp_partition_main_flash_region_safe(start_addr, size)) {
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//ESP_OK = 0, also means protected==0
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return ESP_OK;
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} else {
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return ESP_ERR_NOT_SUPPORTED;
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}
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}
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static DRAM_ATTR spi1_app_func_arg_t spi1_arg = {
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.host_id = 0, //for SPI1,
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.no_protect = true,
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};
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static DRAM_ATTR spi1_app_func_arg_t main_flash_arg = {
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.host_id = 0, //for SPI1,
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.no_protect = false,
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};
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static app_func_arg_t spi2_arg = {
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.host_id = 1, //for SPI2,
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};
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static app_func_arg_t spi3_arg = {
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.host_id = 2, //for SPI3,
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};
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//for SPI1, we have to disable the cache and interrupts before using the SPI bus
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const DRAM_ATTR esp_flash_os_functions_t esp_flash_spi1_default_os_functions = {
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.start = spi1_start,
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.end = spi1_end,
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.delay_us = delay_us,
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.region_protected = main_flash_region_protected,
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};
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const esp_flash_os_functions_t esp_flash_spi23_default_os_functions = {
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.start = spi23_start,
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.end = spi23_end,
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.delay_us = delay_us,
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};
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esp_err_t esp_flash_init_os_functions(esp_flash_t *chip, int host_id)
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{
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if (host_id == 0) {
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//SPI1
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chip->os_func = &esp_flash_spi1_default_os_functions;
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chip->os_func_data = &spi1_arg;
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} else if (host_id == 1 || host_id == 2) {
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//SPI2,3
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chip->os_func = &esp_flash_spi23_default_os_functions;
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chip->os_func_data = (host_id == 1) ? &spi2_arg : &spi3_arg;
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} else {
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return ESP_ERR_INVALID_ARG;
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}
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return ESP_OK;
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}
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esp_err_t esp_flash_app_init_os_functions(esp_flash_t* chip)
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{
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chip->os_func = &esp_flash_spi1_default_os_functions;
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chip->os_func_data = &main_flash_arg;
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return ESP_OK;
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}
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