377 lines
20 KiB
C
377 lines
20 KiB
C
// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _ESP32_SOC_H_
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#define _ESP32_SOC_H_
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#include "esp_assert.h"
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#endif
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//Register Bits{{
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#define BIT31 0x80000000
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#define BIT30 0x40000000
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#define BIT29 0x20000000
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#define BIT28 0x10000000
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#define BIT27 0x08000000
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#define BIT26 0x04000000
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#define BIT25 0x02000000
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#define BIT24 0x01000000
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#define BIT23 0x00800000
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#define BIT22 0x00400000
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#define BIT21 0x00200000
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#define BIT20 0x00100000
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#define BIT19 0x00080000
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#define BIT18 0x00040000
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#define BIT17 0x00020000
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#define BIT16 0x00010000
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#define BIT15 0x00008000
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#define BIT14 0x00004000
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#define BIT13 0x00002000
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#define BIT12 0x00001000
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#define BIT11 0x00000800
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#define BIT10 0x00000400
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#define BIT9 0x00000200
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#define BIT8 0x00000100
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#define BIT7 0x00000080
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#define BIT6 0x00000040
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#define BIT5 0x00000020
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#define BIT4 0x00000010
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#define BIT3 0x00000008
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#define BIT2 0x00000004
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#define BIT1 0x00000002
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#define BIT0 0x00000001
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//}}
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#define PRO_CPU_NUM (0)
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#define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
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#define DR_REG_SYSTEM_BASE 0x3f4c0000
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#define DR_REG_SENSITIVE_BASE 0x3f4c1000
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#define DR_REG_INTERRUPT_BASE 0x3f4c2000
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#define DR_REG_DMA_COPY_BASE 0x3f4c3000
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#define DR_REG_EXTMEM_BASE 0x3f4c4000
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#define DR_REG_MMU_TABLE 0x3f4c5000
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#define DR_REG_ITAG_TABLE 0x3f4c6000
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#define DR_REG_DTAG_TABLE 0x3f4c7000
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#define DR_REG_AES_BASE 0x3f4c8000
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#define DR_REG_SHA_BASE 0x3f4c9000
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#define DR_REG_RSA_BASE 0x3f4ca000
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#define DR_REG_SECURE_BOOT_BASE 0x3f4cb000
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#define DR_REG_HMAC_BASE 0x3f4cc000
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#define DR_REG_DIGITAL_SINGNATURE_BASE 0x3f4cd000
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#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000
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#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000
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#define DR_REG_INTRUSION_BASE 0x3f4d0000
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#define DR_REG_DPORT_END 0x3f4d3FFC
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#define DR_REG_UART_BASE 0x3f400000
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#define DR_REG_SPI1_BASE 0x3f402000
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#define DR_REG_SPI0_BASE 0x3f403000
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#define DR_REG_GPIO_BASE 0x3f404000
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#define DR_REG_GPIO_SD_BASE 0x3f404f00
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#define DR_REG_FE2_BASE 0x3f405000
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#define DR_REG_FE_BASE 0x3f406000
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#define DR_REG_FRC_TIMER_BASE 0x3f407000
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#define DR_REG_RTCCNTL_BASE 0x3f408000
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#define DR_REG_RTCIO_BASE 0x3f408400
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#define DR_REG_SENS_BASE 0x3f408800
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#define DR_REG_RTC_I2C_BASE 0x3f408C00
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#define DR_REG_IO_MUX_BASE 0x3f409000
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#define DR_REG_HINF_BASE 0x3f40B000
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#define DR_REG_I2S_BASE 0x3f40F000
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#define DR_REG_UART1_BASE 0x3f410000
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#define DR_REG_I2C_EXT_BASE 0x3f413000
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#define DR_REG_UHCI0_BASE 0x3f414000
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#define DR_REG_SLCHOST_BASE 0x3f415000
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#define DR_REG_RMT_BASE 0x3f416000
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#define DR_REG_PCNT_BASE 0x3f417000
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#define DR_REG_SLC_BASE 0x3f418000
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#define DR_REG_LEDC_BASE 0x3f419000
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#define DR_REG_EFUSE_BASE 0x3f41A000
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#define DR_REG_NRX_BASE 0x3f41CC00
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#define DR_REG_BB_BASE 0x3f41D000
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#define DR_REG_TIMERGROUP0_BASE 0x3f41F000
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#define DR_REG_TIMERGROUP1_BASE 0x3f420000
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#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000
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#define DR_REG_SPI2_BASE 0x3f424000
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#define DR_REG_SPI3_BASE 0x3f425000
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#define DR_REG_SYSCON_BASE 0x3f426000
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#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */
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#define DR_REG_I2C1_EXT_BASE 0x3f427000
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#define DR_REG_SPI4_BASE 0x3f437000
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#define DR_REG_USB_WRAP_BASE 0x3f439000
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#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE)
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#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 )
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#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 )
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#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
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#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
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#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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#ifndef __ASSEMBLER__
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#define BIT(nr) (1UL << (nr))
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#else
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#define BIT(nr) (1 << (nr))
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#endif
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#ifndef __ASSEMBLER__
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#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
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#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
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#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
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#else
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#define ASSERT_IF_DPORT_REG(_r, OP)
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#endif
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//write value to register
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#define REG_WRITE(_r, _v) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_WRITE); \
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(*(volatile uint32_t *)(_r)) = (_v); \
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})
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//read value from register
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#define REG_READ(_r) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_READ); \
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(*(volatile uint32_t *)(_r)); \
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})
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//get bit or get bits from register
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#define REG_GET_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \
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(*(volatile uint32_t*)(_r) & (_b)); \
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})
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//set bit or set bits to register
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#define REG_SET_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \
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(*(volatile uint32_t*)(_r) |= (_b)); \
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})
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//clear bit or clear bits of register
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#define REG_CLR_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \
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(*(volatile uint32_t*)(_r) &= ~(_b)); \
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})
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//set bits of register controlled by mask
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#define REG_SET_BITS(_r, _b, _m) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \
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(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
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})
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//get field from register, uses field _S & _V to determine mask
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#define REG_GET_FIELD(_r, _f) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \
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((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
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})
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//set field of a register from variable, uses field _S & _V to determine mask
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#define REG_SET_FIELD(_r, _f, _v) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \
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(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
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})
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//get field value from a variable, used when _f is not left shifted by _f##_S
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#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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//get field value from a variable, used when _f is left shifted by _f##_S
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#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
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//set field value to a variable, used when _f is not left shifted by _f##_S
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#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
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//set field value to a variable, used when _f is left shifted by _f##_S
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#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
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//generate a value from a field value, used when _f is not left shifted by _f##_S
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#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
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//generate a value from a field value, used when _f is left shifted by _f##_S
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#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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//read value from register
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#define READ_PERI_REG(addr) ({ \
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ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
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})
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//write value to register
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#define WRITE_PERI_REG(addr, val) ({ \
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ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
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})
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//clear bits of register controlled by mask
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#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
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ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \
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WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
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})
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//set bits of register controlled by mask
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#define SET_PERI_REG_MASK(reg, mask) ({ \
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ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \
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WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
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})
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//get bits of register controlled by mask
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#define GET_PERI_REG_MASK(reg, mask) ({ \
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ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \
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(READ_PERI_REG(reg) & (mask)); \
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})
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//get bits of register controlled by highest bit and lowest bit
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#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
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ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \
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((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
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})
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//set bits of register controlled by mask and shift
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#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
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ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \
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(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
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})
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//get field of register
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#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
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ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \
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((READ_PERI_REG(reg)>>(shift))&(mask)); \
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})
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#endif /* !__ASSEMBLER__ */
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//}}
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//Periheral Clock {{
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#define APB_CLK_FREQ_ROM ( 40*1000000 )
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#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
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#define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM
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#define CPU_CLK_FREQ APB_CLK_FREQ
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#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
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#define REF_CLK_FREQ ( 1000000 )
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#define UART_CLK_FREQ APB_CLK_FREQ
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#define WDT_CLK_FREQ APB_CLK_FREQ
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#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
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#define SPI_CLK_DIV 4
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#define TICKS_PER_US_ROM 40 // CPU is 80MHz
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//}}
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/* Overall memory map */
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#define SOC_DROM_LOW 0x3F000000
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#define SOC_DROM_HIGH 0x3F400000
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#define SOC_IROM_LOW 0x40080000
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#define SOC_IROM_HIGH 0x40c00000
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#define SOC_IRAM_LOW 0x40020000
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#define SOC_IRAM_HIGH 0x40070000
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#define SOC_DRAM_LOW 0x3FFD0000
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#define SOC_DRAM_HIGH 0x3FF80000 // TODO: check RAM ranges
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#define SOC_RTC_IRAM_LOW 0x40070000
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#define SOC_RTC_IRAM_HIGH 0x40072000
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#define SOC_RTC_DRAM_LOW 0x3ff9e000
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#define SOC_RTC_DRAM_HIGH 0x3ffa0000
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#define SOC_RTC_DATA_LOW 0x50000000
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#define SOC_RTC_DATA_HIGH 0x50002000
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#define SOC_EXTRAM_DATA_LOW 0x3F500000
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#define SOC_EXTRAM_DATA_HIGH 0x3FF90000
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#define SOC_SLOW_EXTRAM_DATA_LOW 0x61800000
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#define SOC_SLOW_EXTRAM_DATA_HIGH 0x61c00000
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//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
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#define SOC_DIRAM_IRAM_LOW 0x40020000
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#define SOC_DIRAM_IRAM_HIGH 0x4006FFFC
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#define SOC_DIRAM_DRAM_LOW 0x3FFB0000
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#define SOC_DIRAM_DRAM_HIGH 0x3FFFFFFC
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// Region of memory accessible via DMA. See esp_ptr_dma_capable().
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#define SOC_DMA_LOW 0x3FFB0000
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#define SOC_DMA_HIGH 0x40000000
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// Region of memory that is byte-accessible. See esp_ptr_byte_accessible().
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#define SOC_BYTE_ACCESSIBLE_LOW 0x3FF9E000
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#define SOC_BYTE_ACCESSIBLE_HIGH 0x40000000
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//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
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//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
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#define SOC_MEM_INTERNAL_LOW 0x3FF9E000
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#define SOC_MEM_INTERNAL_HIGH 0x40072000
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//interrupt cpu using table, Please see the core-isa.h
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/*************************************************************************************************************
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* Intr num Level Type PRO CPU usage APP CPU uasge
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* 0 1 extern level WMAC Reserved
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* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
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* 2 1 extern level
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* 3 1 extern level
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* 4 1 extern level WBB
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* 5 1 extern level BT/BLE Controller BT/BLE Controller
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* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
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* 7 1 software BT/BLE VHCI BT/BLE VHCI
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* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
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* 9 1 extern level
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* 10 1 extern edge
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* 11 3 profiling
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* 12 1 extern level
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* 13 1 extern level
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* 14 7 nmi Reserved Reserved
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* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
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* 16 5 timer
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* 17 1 extern level
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* 18 1 extern level
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* 19 2 extern level
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* 20 2 extern level
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* 21 2 extern level
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* 22 3 extern edge
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* 23 3 extern level
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* 24 4 extern level TG1_WDT
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* 25 4 extern level CACHEERR
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* 26 5 extern level
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* 27 3 extern level Reserved Reserved
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* 28 4 extern edge DPORT ACCESS DPORT ACCESS
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* 29 3 software Reserved Reserved
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* 30 4 extern edge Reserved Reserved
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* 31 5 extern level
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*************************************************************************************************************
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*/
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//CPU0 Interrupt number reserved, not touch this.
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#define ETS_WMAC_INUM 0
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#define ETS_BT_HOST_INUM 1
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#define ETS_WBB_INUM 4
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#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
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#define ETS_FRC1_INUM 22
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#define ETS_T1_WDT_INUM 24
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#define ETS_CACHEERR_INUM 25
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#define ETS_DPORT_INUM 28
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//CPU0 Interrupt number used in ROM, should be cancelled in SDK
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#define ETS_SLC_INUM 1
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#define ETS_UART0_INUM 5
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#define ETS_UART1_INUM 5
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//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
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#define ETS_FRC_TIMER2_INUM 10 /* use edge*/
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#define ETS_GPIO_INUM 4
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//Other interrupt number should be managed by the user
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//Invalid interrupt for number interrupt matrix
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#define ETS_INVALID_INUM 6
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#endif /* _ESP32_SOC_H_ */
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