395 lines
11 KiB
C
395 lines
11 KiB
C
/*
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* ESP32 hardware accelerated SHA1/256/512 implementation
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* based on mbedTLS FIPS-197 compliant version.
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*
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* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
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* Additions Copyright (C) 2016-2020, Espressif Systems (Shanghai) PTE Ltd
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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/*
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* The SHA-1 standard was published by NIST in 1993.
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*
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* http://www.itl.nist.gov/fipspubs/fip180-1.htm
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*/
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#include <string.h>
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#include <stdio.h>
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#include <sys/lock.h>
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#include "esp_log.h"
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#include "esp_crypto_lock.h"
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#include "esp32s2/rom/cache.h"
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#include "esp32s2/rom/lldesc.h"
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#include "esp32s2/rom/ets_sys.h"
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#include "soc/crypto_dma_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/hwcrypto_reg.h"
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#include "soc/cache_memory.h"
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#include "soc/periph_defs.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "driver/periph_ctrl.h"
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#include "sys/param.h"
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#include "esp32s2/sha.h"
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/* Max amount of bytes in a single DMA operation is 4095,
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for SHA this means that the biggest safe amount of bytes is
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31 blocks of 128 bytes = 3968
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*/
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#define SHA_DMA_MAX_BYTES 3968
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/* The longest length of a single block is for SHA512 = 128 byte */
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#define SHA_MAX_BLK_LEN 128
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const static char *TAG = "esp-sha";
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/* Return block size (in bytes) for a given SHA type */
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inline static size_t block_length(esp_sha_type type)
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{
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switch (type) {
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case SHA1:
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case SHA2_224:
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case SHA2_256:
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return 64;
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case SHA2_384:
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case SHA2_512:
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case SHA2_512224:
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case SHA2_512256:
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case SHA2_512T:
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return 128;
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default:
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return 0;
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}
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}
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/* Return state size (in bytes) for a given SHA type */
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inline static size_t state_length(esp_sha_type type)
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{
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switch (type) {
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case SHA1:
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return 160 / 8;
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case SHA2_224:
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case SHA2_256:
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return 256 / 8;
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case SHA2_384:
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case SHA2_512:
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case SHA2_512224:
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case SHA2_512256:
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case SHA2_512T:
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return 512 / 8;
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default:
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return 0;
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}
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}
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/* Enable SHA peripheral and then lock it */
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void esp_sha_acquire_hardware()
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{
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esp_crypto_dma_lock_acquire();
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/* Enable SHA and DMA hardware */
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periph_module_enable(PERIPH_SHA_DMA_MODULE);
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/* DMA for SHA */
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REG_WRITE(CRYPTO_DMA_AES_SHA_SELECT_REG, 1);
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}
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/* Disable SHA peripheral block and then release it */
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void esp_sha_release_hardware()
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{
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/* Disable SHA and DMA hardware */
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periph_module_disable(PERIPH_SHA_DMA_MODULE);
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esp_crypto_dma_lock_release();
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}
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/* Busy wait until SHA is idle */
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static void esp_sha_wait_idle(void)
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{
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while (DPORT_REG_READ(SHA_BUSY_REG) != 0) {
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}
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}
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void esp_sha_write_digest_state(esp_sha_type sha_type, void *digest_state)
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{
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uint32_t *digest_state_words = (uint32_t *)digest_state;
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uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_BASE);
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for (int i = 0; i < state_length(sha_type) / 4; i++) {
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REG_WRITE(®_addr_buf[i], digest_state_words[i]);
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}
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}
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/* Read the SHA digest from hardware */
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void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state)
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{
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uint32_t *digest_state_words = (uint32_t *)digest_state;
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int word_len = state_length(sha_type) / 4;
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esp_dport_access_read_buffer(digest_state_words, SHA_H_BASE, word_len);
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/* Fault injection check: verify SHA engine actually ran,
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state is not all zeroes.
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*/
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for (int i = 0; i < word_len; i++) {
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if (digest_state_words[i] != 0) {
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return;
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}
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}
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abort(); // SHA peripheral returned all zero state, probably due to fault injection
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}
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/* The initial hash value for SHA512/t is generated according to the
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algorithm described in the TRM, chapter SHA-Accelerator
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*/
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int esp_sha_512_t_init_hash(uint16_t t)
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{
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uint32_t t_string = 0;
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uint8_t t0, t1, t2, t_len;
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if (t == 384) {
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ESP_LOGE(TAG, "Invalid t for SHA512/t, t = %u,cannot be 384", t);
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return -1;
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}
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if (t <= 9) {
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t_string = (uint32_t)((1 << 23) | ((0x30 + t) << 24));
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t_len = 0x48;
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} else if (t <= 99) {
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t0 = t % 10;
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t1 = (t / 10) % 10;
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t_string = (uint32_t)((1 << 15) | ((0x30 + t0) << 16) |
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(((0x30 + t1) << 24)));
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t_len = 0x50;
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} else if (t <= 512) {
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t0 = t % 10;
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t1 = (t / 10) % 10;
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t2 = t / 100;
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t_string = (uint32_t)((1 << 7) | ((0x30 + t0) << 8) |
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(((0x30 + t1) << 16) + ((0x30 + t2) << 24)));
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t_len = 0x58;
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} else {
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ESP_LOGE(TAG, "Invalid t for SHA512/t, t = %u, must equal or less than 512", t);
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return -1;
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}
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REG_WRITE(SHA_T_LENGTH_REG, t_len);
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REG_WRITE(SHA_T_STRING_REG, t_string);
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REG_WRITE(SHA_MODE_REG, SHA2_512T);
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REG_WRITE(SHA_START_REG, 1);
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esp_sha_wait_idle();
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return 0;
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}
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static void esp_sha_fill_text_block(esp_sha_type sha_type, const void *input)
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{
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uint32_t *reg_addr_buf = (uint32_t *)(SHA_TEXT_BASE);
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uint32_t *data_words = NULL;
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/* Fill the data block */
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data_words = (uint32_t *)(input);
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for (int i = 0; i < block_length(sha_type) / 4; i++) {
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reg_addr_buf[i] = (data_words[i]);
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}
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asm volatile ("memw");
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}
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/* Hash a single SHA block */
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static void esp_sha_block(esp_sha_type sha_type, const void *input, bool is_first_block)
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{
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esp_sha_fill_text_block(sha_type, input);
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esp_sha_wait_idle();
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/* Start hashing */
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if (is_first_block) {
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REG_WRITE(SHA_START_REG, 1);
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} else {
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REG_WRITE(SHA_CONTINUE_REG, 1);
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}
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}
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/* Hash the input block by block, using non-DMA mode */
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static void esp_sha_block_mode(esp_sha_type sha_type, const uint8_t *input, uint32_t ilen,
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const uint8_t *buf, uint32_t buf_len, bool is_first_block)
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{
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size_t blk_len = 0;
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int num_block = 0;
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blk_len = block_length(sha_type);
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REG_WRITE(SHA_MODE_REG, sha_type);
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num_block = ilen / blk_len;
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if (buf_len != 0) {
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esp_sha_block(sha_type, buf, is_first_block);
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is_first_block = false;
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}
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for (int i = 0; i < num_block; i++) {
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esp_sha_block(sha_type, input + blk_len*i, is_first_block);
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is_first_block = false;
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}
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esp_sha_wait_idle();
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}
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static int esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
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const void *buf, uint32_t buf_len, bool is_first_block);
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/* Performs SHA on multiple blocks at a time using DMA
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splits up into smaller operations for inputs that exceed a single DMA list
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*/
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int esp_sha_dma(esp_sha_type sha_type, const void *input, uint32_t ilen,
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const void *buf, uint32_t buf_len, bool is_first_block)
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{
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int ret = 0;
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unsigned char *dma_cap_buf = NULL;
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int dma_op_num = ( ilen / (SHA_DMA_MAX_BYTES + 1) ) + 1;
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if (buf_len > block_length(sha_type)) {
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ESP_LOGE(TAG, "SHA DMA buf_len cannot exceed max size for a single block");
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return -1;
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}
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/* DMA cannot access memory in the iCache range, hash block by block instead of using DMA */
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if (!esp_ptr_dma_ext_capable(input) && !esp_ptr_dma_capable(input) && (ilen != 0)) {
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esp_sha_block_mode(sha_type, input, ilen, buf, buf_len, is_first_block);
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return 0;
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}
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#if (CONFIG_ESP32S2_SPIRAM_SUPPORT)
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if (esp_ptr_external_ram(input)) {
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Cache_WriteBack_Addr((uint32_t)input, ilen);
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}
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if (esp_ptr_external_ram(buf)) {
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Cache_WriteBack_Addr((uint32_t)buf, buf_len);
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}
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#endif
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/* Copy to internal buf if buf is in non DMA capable memory */
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if (!esp_ptr_dma_ext_capable(buf) && !esp_ptr_dma_capable(buf) && (buf_len != 0)) {
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dma_cap_buf = heap_caps_malloc(sizeof(unsigned char) * buf_len, MALLOC_CAP_DMA);
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if (dma_cap_buf == NULL) {
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ESP_LOGE(TAG, "Failed to allocate buf memory");
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ret = -1;
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goto cleanup;
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}
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memcpy(dma_cap_buf, buf, buf_len);
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buf = dma_cap_buf;
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}
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/* The max amount of blocks in a single hardware operation is 2^6 - 1 = 63
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Thus we only do a single DMA input list + dma buf list,
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which is max 3968/64 + 64/64 = 63 blocks */
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for (int i = 0; i < dma_op_num; i++) {
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int dma_chunk_len = MIN(ilen, SHA_DMA_MAX_BYTES);
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ret = esp_sha_dma_process(sha_type, input, dma_chunk_len, buf, buf_len, is_first_block);
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if (ret != 0) {
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goto cleanup;
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}
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ilen -= dma_chunk_len;
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input += dma_chunk_len;
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// Only append buf to the first operation
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buf_len = 0;
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is_first_block = false;
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}
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cleanup:
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free(dma_cap_buf);
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return ret;
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}
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static void esp_sha_dma_init(lldesc_t *input)
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{
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/* Reset DMA */
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SET_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_AHBM_RST | CONF0_REG_OUT_RST | CONF0_REG_AHBM_FIFO_RST);
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CLEAR_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_AHBM_RST | CONF0_REG_OUT_RST | CONF0_REG_AHBM_FIFO_RST);
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/* Set descriptors */
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CLEAR_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, OUT_LINK_REG_OUTLINK_ADDR);
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SET_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, ((uint32_t)(input))&OUT_LINK_REG_OUTLINK_ADDR);
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/* Start transfer */
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SET_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, OUT_LINK_REG_OUTLINK_START);
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}
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/* Performs SHA on multiple blocks at a time */
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static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
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const void *buf, uint32_t buf_len, bool is_first_block)
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{
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size_t blk_len = 0;
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int ret = 0;
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lldesc_t dma_descr_input = {};
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lldesc_t dma_descr_buf = {};
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lldesc_t *dma_descr_head;
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blk_len = block_length(sha_type);
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REG_WRITE(SHA_MODE_REG, sha_type);
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REG_WRITE(SHA_BLOCK_NUM_REG, ((ilen + buf_len) / blk_len));
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/* DMA descriptor for Memory to DMA-SHA transfer */
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if (ilen) {
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dma_descr_input.length = ilen;
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dma_descr_input.size = ilen;
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dma_descr_input.owner = 1;
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dma_descr_input.eof = 1;
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dma_descr_input.buf = input;
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dma_descr_head = &dma_descr_input;
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}
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/* Check after input to overide head if there is any buf*/
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if (buf_len) {
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dma_descr_buf.length = buf_len;
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dma_descr_buf.size = buf_len;
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dma_descr_buf.owner = 1;
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dma_descr_buf.eof = 1;
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dma_descr_buf.buf = buf;
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dma_descr_head = &dma_descr_buf;
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}
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/* Link DMA lists */
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if (buf_len && ilen) {
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dma_descr_buf.eof = 0;
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dma_descr_buf.empty = (uint32_t)(&dma_descr_input);
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}
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esp_sha_dma_init(dma_descr_head);
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/* Start hashing */
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if (is_first_block) {
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REG_WRITE(SHA_DMA_START_REG, 1);
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} else {
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REG_WRITE(SHA_DMA_CONTINUE_REG, 1);
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}
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esp_sha_wait_idle();
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return ret;
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}
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