79 lines
2.4 KiB
C
79 lines
2.4 KiB
C
#include <stddef.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdio.h>
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#include "unity.h"
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#include "soc/soc.h"
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#include "soc/dport_reg.h"
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#include "eri.h"
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#include "trax.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/portmacro.h"
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#include "freertos/semphr.h"
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#include "freertos/task.h"
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// TODO: move these (and same definitions in trax.c to dport_reg.h)
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#define TRACEMEM_MUX_PROBLK0_APPBLK1 0
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#define TRACEMEM_MUX_BLK0_ONLY 1
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#define TRACEMEM_MUX_BLK1_ONLY 2
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#define TRACEMEM_MUX_PROBLK1_APPBLK0 3
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static uint8_t* s_tracemem_blocks[] = {
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(uint8_t*) 0x3FFFC000,
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(uint8_t*) 0x3FFF8000
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};
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static const size_t TRACEMEM_BLOCK_SIZE = 0x4000;
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typedef struct {
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int block;
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SemaphoreHandle_t done;
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} fill_tracemem_arg_t;
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static void fill_tracemem(void* p)
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{
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fill_tracemem_arg_t* arg = (fill_tracemem_arg_t*) p;
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int coreId = xPortGetCoreID();
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memset(s_tracemem_blocks[arg->block] + coreId * TRACEMEM_BLOCK_SIZE / 2,
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(coreId) ? 0xba:0xab, TRACEMEM_BLOCK_SIZE / 2);
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xSemaphoreGive(arg->done);
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vTaskDelay(1);
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vTaskDelete(NULL);
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}
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TEST_CASE("both CPUs can write to trace block 0", "[trace][ignore]")
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{
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// Configure block 1 as trace memory, enable access via both CPUs
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WRITE_PERI_REG(DPORT_PRO_TRACEMEM_ENA_REG, DPORT_PRO_TRACEMEM_ENA_M);
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WRITE_PERI_REG(DPORT_APP_TRACEMEM_ENA_REG, DPORT_APP_TRACEMEM_ENA_M);
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WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, TRACEMEM_MUX_BLK1_ONLY);
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// Stop trace, if any (on the current CPU)
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eri_write(ERI_TRAX_TRAXCTRL, eri_read(ERI_TRAX_TRAXCTRL) | TRAXCTRL_TRSTP);
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eri_write(ERI_TRAX_TRAXCTRL, TRAXCTRL_TMEN);
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// TODO: make sure trace is not running on the other CPU
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// fill two halves of the first trace mem block
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fill_tracemem_arg_t arg1 = {
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.block = 0,
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.done = xSemaphoreCreateBinary()
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};
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fill_tracemem_arg_t arg2 = {
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.block = 0,
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.done = xSemaphoreCreateBinary()
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};
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xTaskCreatePinnedToCore(&fill_tracemem, "fill1", 2048, &arg1, 3, NULL, 0);
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xTaskCreatePinnedToCore(&fill_tracemem, "fill2", 2048, &arg2, 3, NULL, 1);
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xSemaphoreTake(arg1.done, 1);
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xSemaphoreTake(arg2.done, 1);
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vSemaphoreDelete(arg1.done);
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vSemaphoreDelete(arg2.done);
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// Block 0 is filled with data — configure it as trace memory so that it is accessible via TRAX module
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WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, TRACEMEM_MUX_BLK0_ONLY);
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// Block 1 can now be filled with data
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}
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