301dacfb33
Configurable option to use IRAM as byte accessible memory (in single core mode) using load-store (non-word aligned and non-word size IRAM access specific) exception handlers. This allows to use IRAM for use-cases where certain performance penalty (upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration option has been provided to redirect mbedTLS specific in-out content length buffers to IRAM (in single core mode), allows to save 20KB per TLS connection.
123 lines
3.8 KiB
C
123 lines
3.8 KiB
C
/*
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Test for LoadStore exception handlers. This test performs unaligned load and store in 32bit aligned addresses
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*/
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#include <esp_types.h>
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#include <stdio.h>
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#include <esp_heap_caps.h>
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#include "esp_system.h"
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#include "freertos/xtensa_api.h"
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#include "unity.h"
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#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
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TEST_CASE("LoadStore Exception handler", "[freertos]")
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{
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int32_t val0 = 0xDEADBEEF;
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int32_t val1 = 0xBBAA9988;
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int32_t val2 = 0x77665544;
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int32_t val3 = 0x33221100;
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int8_t val8_0 = val0 & 0xff;
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int8_t val8_1 = val1 & 0xff;
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int8_t val8_2 = val2 & 0xff;
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int8_t val8_3 = val3 & 0xff;
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int16_t val16_0 = val0 & 0xffff;
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int16_t val16_1 = val1 & 0xffff;
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int16_t val16_2 = val2 & 0xffff;
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int16_t val16_3 = val3 & 0xffff;
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uint32_t largest_free = heap_caps_get_largest_free_block(MALLOC_CAP_IRAM_8BIT);
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int8_t *arr = heap_caps_malloc(largest_free * sizeof(int8_t), MALLOC_CAP_IRAM_8BIT);
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TEST_ASSERT(arr != NULL);
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int8_t *arr8 = arr;
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int16_t *arr16 = (int16_t *)arr;
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int32_t *arr32 = (int32_t *)arr;
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for (int i = 0; i < 1024; i++) {
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// LoadStoreError
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uint32_t offset = esp_random() % (largest_free - 20);
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uint32_t offset8, offset16, offset32;
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// Get word aligned offset
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offset8 = offset & ~3;
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offset16 = offset8 / 2;
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offset32 = offset8 / 4;
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arr8[offset8] = val8_0;
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arr8[offset8+1] = val8_1;
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arr8[offset8+2] = val8_2;
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arr8[offset8+3] = val8_3;
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// Just to make sure compiler doesn't read stale data
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asm volatile("memw\n");
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TEST_ASSERT_EQUAL(val8_0, arr8[offset8]);
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TEST_ASSERT_EQUAL(val8_1, arr8[offset8+1]);
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TEST_ASSERT_EQUAL(val8_2, arr8[offset8+2]);
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TEST_ASSERT_EQUAL(val8_3, arr8[offset8+3]);
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arr16[offset16] = val16_0;
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arr16[offset16+1] = val16_1;
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arr16[offset16+2] = val16_2;
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arr16[offset16+3] = val16_3;
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// Just to make sure compiler doesn't read stale data
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asm volatile("memw\n");
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TEST_ASSERT_EQUAL(val16_0, arr16[offset16]);
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TEST_ASSERT_EQUAL(val16_1, arr16[offset16+1]);
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TEST_ASSERT_EQUAL(val16_2, arr16[offset16+2]);
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TEST_ASSERT_EQUAL(val16_3, arr16[offset16+3]);
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// LoadStoreAlignement Error
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// Check that it doesn't write to adjacent bytes
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int8_t *ptr8_0 = (void *)&arr8[offset8];
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int8_t *ptr8_1 = (void *)&arr8[offset8] + 5;
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int8_t *ptr8_2 = (void *)&arr8[offset8] + 10;
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int8_t *ptr8_3 = (void *)&arr8[offset8] + 15;
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*ptr8_0 = 0x73;
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*ptr8_1 = 0x73;
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*ptr8_2 = 0x73;
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*ptr8_3 = 0x73;
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int16_t *ptr16_0 = (void *)&arr16[offset16] + 1;
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int16_t *ptr16_1 = (void *)&arr16[offset16] + 3;
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*ptr16_0 = val16_0;
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*ptr16_1 = val16_1;
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// Just to make sure compiler doesn't read stale data
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asm volatile("memw\n");
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TEST_ASSERT_EQUAL(val16_0, *ptr16_0);
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TEST_ASSERT_EQUAL(0x73, *ptr8_0);
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TEST_ASSERT_EQUAL(val16_1, *ptr16_1);
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TEST_ASSERT_EQUAL(0x73, *ptr8_1);
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int32_t *ptr32_0 = (void *)&arr32[offset32] + 1;
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int32_t *ptr32_1 = (void *)&arr32[offset32] + 6;
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int32_t *ptr32_2 = (void *)&arr32[offset32] + 11;
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*ptr32_0 = val0;
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*ptr32_1 = val1;
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*ptr32_2 = val2;
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// Just to make sure compiler doesn't read stale data
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asm volatile ("memw");
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TEST_ASSERT_EQUAL(0x73, *ptr8_0);
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TEST_ASSERT_EQUAL(val0, *ptr32_0);
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TEST_ASSERT_EQUAL(0x73, *ptr8_1);
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TEST_ASSERT_EQUAL(val1, *ptr32_1);
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TEST_ASSERT_EQUAL(0x73, *ptr8_2);
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TEST_ASSERT_EQUAL(val2, *ptr32_2);
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TEST_ASSERT_EQUAL(0x73, *ptr8_3);
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}
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TEST_ASSERT_TRUE(heap_caps_check_integrity_all(true));
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heap_caps_free(arr);
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}
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#endif
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