176 lines
6.4 KiB
C
176 lines
6.4 KiB
C
// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include "esp_system.h"
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#include "esp_private/system_internal.h"
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#include "esp_attr.h"
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#include "esp_efuse.h"
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#include "esp_wifi.h"
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#include "esp_log.h"
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#include "sdkconfig.h"
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#include "esp32/rom/efuse.h"
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#include "esp32/rom/cache.h"
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#include "esp32/rom/uart.h"
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#include "soc/dport_reg.h"
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#include "soc/gpio_periph.h"
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#include "soc/efuse_periph.h"
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#include "soc/rtc_periph.h"
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#include "soc/timer_periph.h"
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#include "soc/cpu.h"
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#include "soc/rtc.h"
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#include "hal/wdt_hal.h"
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#include "freertos/xtensa_api.h"
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#include "esp32/cache_err_int.h"
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/* "inner" restart function for after RTOS, interrupts & anything else on this
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* core are already stopped. Stalls other core, resets hardware,
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* triggers restart.
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*/
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void IRAM_ATTR esp_restart_noos(void)
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{
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// Disable interrupts
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xt_ints_off(0xFFFFFFFF);
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// Enable RTC watchdog for 1 second
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wdt_hal_context_t rtc_wdt_ctx;
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wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
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uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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// Reset and stall the other CPU.
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// CPU must be reset before stalling, in case it was running a s32c1i
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// instruction. This would cause memory pool to be locked by arbiter
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// to the stalled CPU, preventing current CPU from accessing this pool.
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const uint32_t core_id = xPortGetCoreID();
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const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
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esp_cpu_reset(other_core_id);
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esp_cpu_stall(other_core_id);
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// Other core is now stalled, can access DPORT registers directly
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esp_dport_access_int_abort();
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//Todo: Refactor to use Interrupt or Task Watchdog API, and a system level WDT context
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// Disable TG0/TG1 watchdogs
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wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
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wdt_hal_write_protect_disable(&wdt0_context);
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wdt_hal_disable(&wdt0_context);
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wdt_hal_write_protect_enable(&wdt0_context);
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wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
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wdt_hal_write_protect_disable(&wdt1_context);
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wdt_hal_disable(&wdt1_context);
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wdt_hal_write_protect_enable(&wdt1_context);
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// Flush any data left in UART FIFOs
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uart_tx_wait_idle(0);
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uart_tx_wait_idle(1);
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uart_tx_wait_idle(2);
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#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
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if (esp_ptr_external_ram(get_sp())) {
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// If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used)
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// then need to switch SP to Internal Memory otherwise
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// we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable.
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uint32_t new_sp = SOC_DRAM_LOW + (SOC_DRAM_HIGH - SOC_DRAM_LOW) / 2;
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SET_STACK(new_sp);
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}
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#endif
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// Disable cache
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Cache_Read_Disable(0);
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Cache_Read_Disable(1);
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// 2nd stage bootloader reconfigures SPI flash signals.
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// Reset them to the defaults expected by ROM.
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WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
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// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
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DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
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DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
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DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
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DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
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DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
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DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
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// Reset timer/spi/uart
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
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//UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here.
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DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST);
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DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
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// Set CPU back to XTAL source, no PLL, same as hard reset
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rtc_clk_cpu_freq_set_xtal();
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// Clear entry point for APP CPU
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DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
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// Reset CPUs
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if (core_id == 0) {
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// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
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esp_cpu_reset(1);
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esp_cpu_reset(0);
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} else {
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// Running on APP CPU: need to reset PRO CPU and unstall it,
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// then reset APP CPU
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esp_cpu_reset(0);
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esp_cpu_unstall(0);
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esp_cpu_reset(1);
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}
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while(true) {
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;
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}
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}
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void esp_chip_info(esp_chip_info_t* out_info)
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{
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uint32_t efuse_rd3 = REG_READ(EFUSE_BLK0_RDATA3_REG);
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memset(out_info, 0, sizeof(*out_info));
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out_info->model = CHIP_ESP32;
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out_info->revision = esp_efuse_get_chip_ver();
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if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) {
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out_info->cores = 2;
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} else {
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out_info->cores = 1;
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}
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out_info->features = CHIP_FEATURE_WIFI_BGN;
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if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
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out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
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}
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int package = (efuse_rd3 & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S;
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if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
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package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
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package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
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out_info->features |= CHIP_FEATURE_EMB_FLASH;
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}
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}
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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inline bool soc_has_cache_lock_bug(void)
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{
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return (esp_efuse_get_chip_ver() == 3);
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}
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#endif
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