742f8e7f8a
1. ref_clock used in unit tests occasionally produces time off by ~100 microseconds shortly after being started. Add a delay to let ref_clock stabilise, until the cause is found. 2. Reduce roundoff error accumulation which would occasionally cause the test to fail, by choosing an overflow value which can be divided by APB frequency. 3. Move time sampling part of the test into an IRAM function to reduce variations due to cache behavior. 4. Remove calculation of "standard deviation" in the test, as what was calculated was not actually standard deviation, and it did not add any useful information.
406 lines
16 KiB
C
406 lines
16 KiB
C
// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp_err.h"
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#include "esp_timer.h"
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#include "esp_system.h"
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#include "esp_task.h"
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#include "esp_attr.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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#include "esp_clk.h"
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#include "esp_timer_impl.h"
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#include "soc/frc_timer_reg.h"
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#include "soc/rtc.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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/**
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* @file esp_timer_esp32.c
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* @brief Implementation of chip-specific part of esp_timer
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*
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* This implementation uses FRC2 (legacy) timer of the ESP32. This timer is
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* a 32-bit up-counting timer, with a programmable compare value (called 'alarm'
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* hereafter). When the timer reaches compare value, interrupt is raised.
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* The timer can be configured to produce an edge or a level interrupt.
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*
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* In this implementation the timer is used for two purposes:
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* 1. To generate interrupts at certain moments — the upper layer of esp_timer
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* uses this to trigger callbacks of esp_timer objects.
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*
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* 2. To keep track of time relative to application start. This facility is
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* used both by the upper layer of esp_timer and by time functions, such as
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* gettimeofday.
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*
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* Whenever an esp_timer timer is armed (configured to fire once or
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* periodically), timer_insert function of the upper layer calls
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* esp_timer_impl_set_alarm to enable the interrupt at the required moment.
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* This implementation sets up the timer interrupt to fire at the earliest of
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* two moments:
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* a) the time requested by upper layer
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* b) the time when the timer count reaches 0xffffffff (i.e. is about to overflow)
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*
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* Whenever the interrupt fires and timer overflow is detected, interrupt hander
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* increments s_time_base_us variable, which is used for timekeeping.
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*
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* When the interrupt fires, the upper layer is notified, and it dispatches
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* the callbacks (if any timers have expired) and sets new alarm value (if any
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* timers are still active).
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*
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* At any point in time, esp_timer_impl_get_time will return the current timer
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* value (expressed in microseconds) plus s_time_base_us. To account for the
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* case when the timer counter has overflown, but the interrupt has not fired
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* yet (for example, because interupts are temporarily disabled),
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* esp_timer_impl_get_time will also check timer overflow flag, and will add
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* s_timer_us_per_overflow to the returned value.
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*
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*/
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/* Timer is clocked from APB. To allow for integer scaling factor between ticks
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* and microseconds, divider 1 is used. 16 or 256 would not work for APB
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* frequencies such as 40 or 26 or 2 MHz.
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*/
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#define TIMER_DIV 1
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#define TIMER_DIV_CFG FRC_TIMER_PRESCALER_1
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/* ALARM_OVERFLOW_VAL is used as timer alarm value when there are not timers
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* enabled which need to fire within the next timer overflow period. This alarm
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* is used to perform timekeeping (i.e. to track timer overflows).
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* Due to the 0xffffffff cannot recognize the real overflow or the scenario that
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* ISR happens follow set_alarm, so change the ALARM_OVERFLOW_VAL to resolve this problem.
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* Set it to 0xefffffffUL. The remain 0x10000000UL(about 3 second) is enough to handle ISR.
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*/
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#define DEFAULT_ALARM_OVERFLOW_VAL 0xefffffffUL
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/* Provision to set lower overflow value for unit testing. Lowering the
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* overflow value helps check for race conditions which occur near overflow
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* moment.
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*/
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#ifndef ESP_TIMER_DYNAMIC_OVERFLOW_VAL
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#define ALARM_OVERFLOW_VAL DEFAULT_ALARM_OVERFLOW_VAL
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#else
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static uint32_t s_alarm_overflow_val = DEFAULT_ALARM_OVERFLOW_VAL;
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#define ALARM_OVERFLOW_VAL (s_alarm_overflow_val)
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#endif
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static const char* TAG = "esp_timer_impl";
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// Interrupt handle returned by the interrupt allocator
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static intr_handle_t s_timer_interrupt_handle;
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// Function from the upper layer to be called when the interrupt happens.
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// Registered in esp_timer_impl_init.
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static intr_handler_t s_alarm_handler;
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// Time in microseconds from startup to the moment
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// when timer counter was last equal to 0. This variable is updated each time
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// when timer overflows, and when APB frequency switch is performed.
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static uint64_t s_time_base_us;
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// Number of timer ticks per microsecond. Calculated from APB frequency.
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static uint32_t s_timer_ticks_per_us;
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// Period between timer overflows, in microseconds.
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// Equal to 2^32 / s_timer_ticks_per_us.
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static uint32_t s_timer_us_per_overflow;
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// When frequency switch happens, timer counter is reset to 0, s_time_base_us
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// is updated, and alarm value is re-calculated based on the new APB frequency.
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// However because the frequency switch can happen before the final
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// interrupt handler is invoked, interrupt handler may see a different alarm
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// value than the one which caused an interrupt. This can cause interrupt handler
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// to consider that the interrupt has happened due to timer overflow, incrementing
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// s_time_base_us. To avoid this, frequency switch hook sets this flag if
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// it needs to set timer alarm value to ALARM_OVERFLOW_VAL. Interrupt handler
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// will not increment s_time_base_us if this flag is set.
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static bool s_mask_overflow;
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//The timer_overflow_happened read alarm register to tell if overflow happened.
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//However, there is a monent that overflow happens, and before ISR function called
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//alarm register is set to another value, then you call timer_overflow_happened,
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//it will return false.
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//So we store the overflow value when new alarm is to be set.
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static bool s_overflow_happened;
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#ifdef CONFIG_PM_DFS_USE_RTC_TIMER_REF
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// If DFS is enabled, upon the first frequency change this value is set to the
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// difference between esp_timer value and RTC timer value. On every subsequent
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// frequency change, s_time_base_us is adjusted to maintain the same difference
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// between esp_timer and RTC timer. (All mentioned values are in microseconds.)
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static uint64_t s_rtc_time_diff = 0;
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#endif
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// Spinlock used to protect access to static variables above and to the hardware
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// registers.
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portMUX_TYPE s_time_update_lock = portMUX_INITIALIZER_UNLOCKED;
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//Use FRC_TIMER_LOAD_VALUE(1) instead of UINT32_MAX, convenience to change FRC TIMER for future
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#define TIMER_IS_AFTER_OVERFLOW(a) (ALARM_OVERFLOW_VAL < (a) && (a) <= FRC_TIMER_LOAD_VALUE(1))
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// Check if timer overflow has happened (but was not handled by ISR yet)
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static inline bool IRAM_ATTR timer_overflow_happened()
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{
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if (s_overflow_happened) {
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return true;
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}
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return ((REG_READ(FRC_TIMER_CTRL_REG(1)) & FRC_TIMER_INT_STATUS) != 0 &&
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((REG_READ(FRC_TIMER_ALARM_REG(1)) == ALARM_OVERFLOW_VAL && TIMER_IS_AFTER_OVERFLOW(REG_READ(FRC_TIMER_COUNT_REG(1))) && !s_mask_overflow) ||
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(!TIMER_IS_AFTER_OVERFLOW(REG_READ(FRC_TIMER_ALARM_REG(1))) && TIMER_IS_AFTER_OVERFLOW(REG_READ(FRC_TIMER_COUNT_REG(1))))));
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}
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static inline void IRAM_ATTR timer_count_reload(void)
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{
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//this function should be only called the real overflow happened. And the count cannot be very approach to 0xffffffff.
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assert(TIMER_IS_AFTER_OVERFLOW(REG_READ(FRC_TIMER_COUNT_REG(1))));
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/* Restart the timer count by current time count minus ALARM_OVERFLOW_VAL(0xefffffff), it may cause error, if current tick is near boundary.
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* But even if the error happen 100% per overflow(the distance of each real overflow is about 50 second),
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* the error is 0.0125us*N per 50s(the FRC time clock is 80MHz), the N is the ticks run by the line following,
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* Normally, N is less than 10, assume N is 10, so the error accumulation is only 6.48ms per month.
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* In fact, if the CPU frequency is large than 80MHz. The error accumulation will be more less than 6.48ms per month.
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* so It can be adopted.
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*/
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REG_WRITE(FRC_TIMER_LOAD_REG(1), REG_READ(FRC_TIMER_COUNT_REG(1)) - ALARM_OVERFLOW_VAL);
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}
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void esp_timer_impl_lock()
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{
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portENTER_CRITICAL(&s_time_update_lock);
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}
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void esp_timer_impl_unlock()
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{
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portEXIT_CRITICAL(&s_time_update_lock);
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}
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uint64_t IRAM_ATTR esp_timer_impl_get_time()
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{
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uint32_t timer_val;
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uint64_t time_base;
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uint32_t ticks_per_us;
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bool overflow;
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do {
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/* Read all values needed to calculate current time */
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timer_val = REG_READ(FRC_TIMER_COUNT_REG(1));
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time_base = s_time_base_us;
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overflow = timer_overflow_happened();
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ticks_per_us = s_timer_ticks_per_us;
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/* Read them again and compare */
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/* In this function, do not call timer_count_reload() when overflow is true.
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* Because there's remain count enough to allow FRC_TIMER_COUNT_REG grow
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*/
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if (REG_READ(FRC_TIMER_COUNT_REG(1)) > timer_val &&
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time_base == *((volatile uint64_t*) &s_time_base_us) &&
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ticks_per_us == *((volatile uint32_t*) &s_timer_ticks_per_us) &&
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overflow == timer_overflow_happened()) {
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break;
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}
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/* If any value has changed (other than the counter increasing), read again */
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} while(true);
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uint64_t result = time_base
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+ timer_val / ticks_per_us;
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return result;
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}
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void IRAM_ATTR esp_timer_impl_set_alarm(uint64_t timestamp)
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{
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portENTER_CRITICAL(&s_time_update_lock);
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// Alarm time relative to the moment when counter was 0
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uint64_t time_after_timebase_us = timestamp - s_time_base_us;
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// Adjust current time if overflow has happened
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bool overflow = timer_overflow_happened();
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uint64_t cur_count = REG_READ(FRC_TIMER_COUNT_REG(1));
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if (overflow) {
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assert(time_after_timebase_us > s_timer_us_per_overflow);
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time_after_timebase_us -= s_timer_us_per_overflow;
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s_overflow_happened = true;
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}
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// Calculate desired timer compare value (may exceed 2^32-1)
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uint64_t compare_val = time_after_timebase_us * s_timer_ticks_per_us;
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uint32_t alarm_reg_val = ALARM_OVERFLOW_VAL;
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// Use calculated alarm value if it is less than ALARM_OVERFLOW_VAL.
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// Note that if by the time we update ALARM_REG, COUNT_REG value is higher,
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// interrupt will not happen for another ALARM_OVERFLOW_VAL timer ticks,
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// so need to check if alarm value is too close in the future (e.g. <2 us away).
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const uint32_t offset = s_timer_ticks_per_us * 2;
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if (compare_val < ALARM_OVERFLOW_VAL) {
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if (compare_val < cur_count + offset) {
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compare_val = cur_count + offset;
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if (compare_val > ALARM_OVERFLOW_VAL) {
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compare_val = ALARM_OVERFLOW_VAL;
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}
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}
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alarm_reg_val = (uint32_t) compare_val;
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}
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REG_WRITE(FRC_TIMER_ALARM_REG(1), alarm_reg_val);
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portEXIT_CRITICAL(&s_time_update_lock);
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}
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static void IRAM_ATTR timer_alarm_isr(void *arg)
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{
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portENTER_CRITICAL_ISR(&s_time_update_lock);
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// Timekeeping: adjust s_time_base_us if counter has passed ALARM_OVERFLOW_VAL
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if (timer_overflow_happened()) {
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timer_count_reload();
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s_time_base_us += s_timer_us_per_overflow;
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s_overflow_happened = false;
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}
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s_mask_overflow = false;
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// Clear interrupt status
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REG_WRITE(FRC_TIMER_INT_REG(1), FRC_TIMER_INT_CLR);
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// Set alarm to the next overflow moment. Later, upper layer function may
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// call esp_timer_impl_set_alarm to change this to an earlier value.
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REG_WRITE(FRC_TIMER_ALARM_REG(1), ALARM_OVERFLOW_VAL);
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portEXIT_CRITICAL_ISR(&s_time_update_lock);
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// Call the upper layer handler
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(*s_alarm_handler)(arg);
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}
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void IRAM_ATTR esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us)
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{
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portENTER_CRITICAL_ISR(&s_time_update_lock);
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/* Bail out if the timer is not initialized yet */
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if (s_timer_interrupt_handle == NULL) {
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portEXIT_CRITICAL_ISR(&s_time_update_lock);
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return;
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}
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uint32_t new_ticks_per_us = apb_ticks_per_us / TIMER_DIV;
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uint32_t alarm = REG_READ(FRC_TIMER_ALARM_REG(1));
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uint32_t count = REG_READ(FRC_TIMER_COUNT_REG(1));
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uint64_t ticks_to_alarm = alarm - count;
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uint64_t new_ticks = (ticks_to_alarm * new_ticks_per_us) / s_timer_ticks_per_us;
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uint32_t new_alarm_val;
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if (alarm > count && new_ticks <= ALARM_OVERFLOW_VAL) {
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new_alarm_val = new_ticks;
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} else {
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new_alarm_val = ALARM_OVERFLOW_VAL;
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if (alarm != ALARM_OVERFLOW_VAL) {
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s_mask_overflow = true;
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}
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}
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REG_WRITE(FRC_TIMER_ALARM_REG(1), new_alarm_val);
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REG_WRITE(FRC_TIMER_LOAD_REG(1), 0);
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s_time_base_us += count / s_timer_ticks_per_us;
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#ifdef CONFIG_PM_DFS_USE_RTC_TIMER_REF
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// Due to the extra time required to read RTC time, don't attempt this
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// adjustment when switching to a higher frequency (which usually
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// happens in an interrupt).
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if (new_ticks_per_us < s_timer_ticks_per_us) {
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uint64_t rtc_time = esp_clk_rtc_time();
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uint64_t new_rtc_time_diff = s_time_base_us - rtc_time;
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if (s_rtc_time_diff != 0) {
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uint64_t correction = new_rtc_time_diff - s_rtc_time_diff;
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s_time_base_us -= correction;
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} else {
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s_rtc_time_diff = new_rtc_time_diff;
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}
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}
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#endif // CONFIG_PM_DFS_USE_RTC_TIMER_REF
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s_timer_ticks_per_us = new_ticks_per_us;
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s_timer_us_per_overflow = ALARM_OVERFLOW_VAL / new_ticks_per_us;
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portEXIT_CRITICAL_ISR(&s_time_update_lock);
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}
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void esp_timer_impl_advance(int64_t time_us)
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{
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assert(time_us > 0 && "negative adjustments not supported yet");
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portENTER_CRITICAL(&s_time_update_lock);
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uint64_t count = REG_READ(FRC_TIMER_COUNT_REG(1));
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/* Trigger an ISR to handle past alarms and set new one.
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* ISR handler will run once we exit the critical section.
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*/
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REG_WRITE(FRC_TIMER_ALARM_REG(1), 0);
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REG_WRITE(FRC_TIMER_LOAD_REG(1), 0);
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s_time_base_us += count / s_timer_ticks_per_us + time_us;
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s_overflow_happened = false;
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portEXIT_CRITICAL(&s_time_update_lock);
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}
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esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler)
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{
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s_alarm_handler = alarm_handler;
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esp_err_t err = esp_intr_alloc(ETS_TIMER2_INTR_SOURCE,
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ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_IRAM,
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&timer_alarm_isr, NULL, &s_timer_interrupt_handle);
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if (err != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "esp_intr_alloc failed (0x%0x)", err);
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return err;
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}
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uint32_t apb_freq = rtc_clk_apb_freq_get();
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s_timer_ticks_per_us = apb_freq / 1000000 / TIMER_DIV;
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assert(s_timer_ticks_per_us > 0
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&& apb_freq % TIMER_DIV == 0
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&& "APB frequency does not result in a valid ticks_per_us value");
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s_timer_us_per_overflow = ALARM_OVERFLOW_VAL / s_timer_ticks_per_us;
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s_time_base_us = 0;
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REG_WRITE(FRC_TIMER_ALARM_REG(1), ALARM_OVERFLOW_VAL);
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REG_WRITE(FRC_TIMER_LOAD_REG(1), 0);
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REG_WRITE(FRC_TIMER_CTRL_REG(1),
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TIMER_DIV_CFG | FRC_TIMER_ENABLE | FRC_TIMER_LEVEL_INT);
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REG_WRITE(FRC_TIMER_INT_REG(1), FRC_TIMER_INT_CLR);
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ESP_ERROR_CHECK( esp_intr_enable(s_timer_interrupt_handle) );
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return ESP_OK;
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}
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void esp_timer_impl_deinit()
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{
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esp_intr_disable(s_timer_interrupt_handle);
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REG_WRITE(FRC_TIMER_CTRL_REG(1), 0);
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REG_WRITE(FRC_TIMER_ALARM_REG(1), 0);
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REG_WRITE(FRC_TIMER_LOAD_REG(1), 0);
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esp_intr_free(s_timer_interrupt_handle);
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s_timer_interrupt_handle = NULL;
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}
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// FIXME: This value is safe for 80MHz APB frequency.
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// Should be modified to depend on clock frequency.
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uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us()
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{
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return 50;
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}
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#ifdef ESP_TIMER_DYNAMIC_OVERFLOW_VAL
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uint32_t esp_timer_impl_get_overflow_val()
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{
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return s_alarm_overflow_val;
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}
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void esp_timer_impl_set_overflow_val(uint32_t overflow_val)
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{
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s_alarm_overflow_val = overflow_val;
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/* update alarm value */
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esp_timer_impl_update_apb_freq(esp_clk_apb_freq() / 1000000);
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}
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#endif // ESP_TIMER_DYNAMIC_OVERFLOW_VAL
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