150 lines
5.5 KiB
C
150 lines
5.5 KiB
C
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_eth.h"
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#include "eth_phy/phy_lan8720.h"
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#include "eth_phy/phy_reg.h"
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/* Value of MII_PHY_IDENTIFIER_REGs for Microchip LAN8720
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* (Except for bottom 4 bits of ID2, used for model revision)
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*/
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#define LAN8720_PHY_ID1 0x0007
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#define LAN8720_PHY_ID2 0xc0f0
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#define LAN8720_PHY_ID2_MASK 0xFFF0
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/* LAN8720-specific registers */
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#define SW_STRAP_CONTROL_REG (0x9)
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#define SW_STRAP_CONFIG_DONE BIT(15)
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#define AUTO_MDIX_ENABLE BIT(14)
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#define AUTO_NEGOTIATION_ENABLE BIT(13)
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#define AN_1 BIT(12)
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#define AN_0 BIT(11)
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#define LED_CFG BIT(10)
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#define RMII_ENHANCED_MODE BIT(9)
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#define DEFAULT_STRAP_CONFIG (AUTO_MDIX_ENABLE|AUTO_NEGOTIATION_ENABLE|AN_1|AN_0|LED_CFG)
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#define PHY_SPECIAL_CONTROL_STATUS_REG (0x1f)
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#define AUTO_NEGOTIATION_DONE BIT(12)
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#define SPEED_DUPLEX_INDICATION_10T_HALF 0x04
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#define SPEED_DUPLEX_INDICATION_10T_FULL 0x14
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#define SPEED_DUPLEX_INDICATION_100T_HALF 0x08
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#define SPEED_DUPLEX_INDICATION_100T_FULL 0x18
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#define SPEED_INDICATION_100T BIT(3)
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#define SPEED_INDICATION_10T BIT(2)
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#define DUPLEX_INDICATION_FULL BIT(4)
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static const char *TAG = "lan8720";
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void phy_lan8720_check_phy_init(void)
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{
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phy_lan8720_dump_registers();
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esp_eth_smi_wait_set(MII_BASIC_MODE_STATUS_REG, MII_AUTO_NEGOTIATION_COMPLETE, 0);
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esp_eth_smi_wait_set(PHY_SPECIAL_CONTROL_STATUS_REG, AUTO_NEGOTIATION_DONE, 0);
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}
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eth_speed_mode_t phy_lan8720_get_speed_mode(void)
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{
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if(esp_eth_smi_read(PHY_SPECIAL_CONTROL_STATUS_REG) & SPEED_INDICATION_100T) {
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ESP_LOGD(TAG, "phy_lan8720_get_speed_mode(100)");
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return ETH_SPEED_MODE_100M;
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} else {
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ESP_LOGD(TAG, "phy_lan8720_get_speed_mode(10)");
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return ETH_SPEED_MODE_10M;
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}
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}
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eth_duplex_mode_t phy_lan8720_get_duplex_mode(void)
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{
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if(esp_eth_smi_read(PHY_SPECIAL_CONTROL_STATUS_REG) & DUPLEX_INDICATION_FULL) {
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ESP_LOGD(TAG, "phy_lan8720_get_duplex_mode(FULL)");
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return ETH_MODE_FULLDUPLEX;
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} else {
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ESP_LOGD(TAG, "phy_lan8720_get_duplex_mode(HALF)");
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return ETH_MODE_HALFDUPLEX;
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}
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}
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void phy_lan8720_power_enable(bool enable)
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{
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if (enable) {
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esp_eth_smi_write(SW_STRAP_CONTROL_REG, DEFAULT_STRAP_CONFIG | SW_STRAP_CONFIG_DONE);
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// TODO: only enable if config.flow_ctrl_enable == true
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phy_mii_enable_flow_ctrl();
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}
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}
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void phy_lan8720_init(void)
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{
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ESP_LOGD(TAG, "phy_lan8720_init()");
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phy_lan8720_dump_registers();
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esp_eth_smi_write(MII_BASIC_MODE_CONTROL_REG, MII_SOFTWARE_RESET);
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esp_err_t res1, res2;
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do {
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// Call esp_eth_smi_wait_value() with a timeout so it prints an error periodically
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res1 = esp_eth_smi_wait_value(MII_PHY_IDENTIFIER_1_REG, LAN8720_PHY_ID1, UINT16_MAX, 1000);
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res2 = esp_eth_smi_wait_value(MII_PHY_IDENTIFIER_2_REG, LAN8720_PHY_ID2, LAN8720_PHY_ID2_MASK, 1000);
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} while(res1 != ESP_OK || res2 != ESP_OK);
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esp_eth_smi_write(SW_STRAP_CONTROL_REG,
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DEFAULT_STRAP_CONFIG | SW_STRAP_CONFIG_DONE);
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ets_delay_us(300);
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// TODO: only enable if config.flow_ctrl_enable == true
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phy_mii_enable_flow_ctrl();
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}
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const eth_config_t phy_lan8720_default_ethernet_config = {
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// By default, the PHY address is 0 or 1 based on PHYAD0
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// pin. Can also be overriden in software. See datasheet
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// for defaults.
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.phy_addr = 0,
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.mac_mode = ETH_MODE_RMII,
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.clock_mode = ETH_CLOCK_GPIO0_IN,
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//Only FULLDUPLEX mode support flow ctrl now!
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.flow_ctrl_enable = true,
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.phy_init = phy_lan8720_init,
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.phy_check_init = phy_lan8720_check_phy_init,
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.phy_power_enable = phy_lan8720_power_enable,
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.phy_check_link = phy_mii_check_link_status,
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.phy_get_speed_mode = phy_lan8720_get_speed_mode,
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.phy_get_duplex_mode = phy_lan8720_get_duplex_mode,
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.phy_get_partner_pause_enable = phy_mii_get_partner_pause_enable,
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};
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void phy_lan8720_dump_registers()
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{
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ESP_LOGD(TAG, "LAN8720 Registers:");
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ESP_LOGD(TAG, "BCR 0x%04x", esp_eth_smi_read(0x0));
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ESP_LOGD(TAG, "BSR 0x%04x", esp_eth_smi_read(0x1));
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ESP_LOGD(TAG, "PHY1 0x%04x", esp_eth_smi_read(0x2));
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ESP_LOGD(TAG, "PHY2 0x%04x", esp_eth_smi_read(0x3));
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ESP_LOGD(TAG, "ANAR 0x%04x", esp_eth_smi_read(0x4));
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ESP_LOGD(TAG, "ANLPAR 0x%04x", esp_eth_smi_read(0x5));
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ESP_LOGD(TAG, "ANER 0x%04x", esp_eth_smi_read(0x6));
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ESP_LOGD(TAG, "MCSR 0x%04x", esp_eth_smi_read(0x11));
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ESP_LOGD(TAG, "SM 0x%04x", esp_eth_smi_read(0x12));
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ESP_LOGD(TAG, "SECR 0x%04x", esp_eth_smi_read(0x1A));
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ESP_LOGD(TAG, "CSIR 0x%04x", esp_eth_smi_read(0x1B));
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ESP_LOGD(TAG, "ISR 0x%04x", esp_eth_smi_read(0x1D));
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ESP_LOGD(TAG, "IMR 0x%04x", esp_eth_smi_read(0x1E));
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ESP_LOGD(TAG, "PSCSR 0x%04x", esp_eth_smi_read(0x1F));
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}
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