f7df532ec0
1. External 32kHz crystal is started for too long or it may not start at all. It is often observed at the first start. 2. At the first start, it is possible that the crystal did not start. And the recorded period was recorded as 0. Which led to a division error by zero during the transition to the deep sleep mode (Maybe somewhere else). 3. Added a unit test to test a new method of oscillation an external crystal. 4. Added a new method of oscillating of an external crystal. The legs of the crystal are fed with a 32 kHz frequency. The new method eliminates these errors. Added unit test: `\esp-idf\components\soc\esp32\test\test_rtc_clk.c`: `make TEST_COMPONENTS=soc` - 8 Test starting external RTC crystal. Will pass. `Bootstrap cycles for external 32kHz crystal` - is specified in the file Kconfig by default 100. QA tested a new method of oscillation the crystal on 25 boards. The supply of square waves on the crystal showed a 100% result in contrast to the previous method of launching the crystal. After the tests, the old method was deleted. Closes TW19143
62 lines
2.4 KiB
C
62 lines
2.4 KiB
C
// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
|
|
//
|
|
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
// you may not use this file except in compliance with the License.
|
|
// You may obtain a copy of the License at
|
|
//
|
|
// http://www.apache.org/licenses/LICENSE-2.0
|
|
//
|
|
// Unless required by applicable law or agreed to in writing, software
|
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
// See the License for the specific language governing permissions and
|
|
// limitations under the License.
|
|
#include "rom/uart.h"
|
|
#include "rom/rtc.h"
|
|
#include "soc/soc.h"
|
|
#include "soc/rtc.h"
|
|
#include "soc/dport_reg.h"
|
|
#include "soc/efuse_reg.h"
|
|
#include "soc/rtc_cntl_reg.h"
|
|
|
|
void bootloader_clock_configure()
|
|
{
|
|
// ROM bootloader may have put a lot of text into UART0 FIFO.
|
|
// Wait for it to be printed.
|
|
// This is not needed on power on reset, when ROM bootloader is running at
|
|
// 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
|
|
// and will be done with the bootloader much earlier than UART FIFO is empty.
|
|
uart_tx_wait_idle(0);
|
|
|
|
/* Set CPU to 80MHz. Keep other clocks unmodified. */
|
|
rtc_cpu_freq_t cpu_freq = RTC_CPU_FREQ_80M;
|
|
|
|
/* On ESP32 rev 0, switching to 80MHz if clock was previously set to
|
|
* 240 MHz may cause the chip to lock up (see section 3.5 of the errata
|
|
* document). For rev. 0, switch to 240 instead if it was chosen in
|
|
* menuconfig.
|
|
*/
|
|
uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
|
|
if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 &&
|
|
CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ == 240) {
|
|
cpu_freq = RTC_CPU_FREQ_240M;
|
|
}
|
|
|
|
rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
|
|
clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
|
|
clk_cfg.cpu_freq = cpu_freq;
|
|
clk_cfg.slow_freq = rtc_clk_slow_freq_get();
|
|
clk_cfg.fast_freq = rtc_clk_fast_freq_get();
|
|
rtc_clk_init(clk_cfg);
|
|
/* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable
|
|
* it here. Usually it needs some time to start up, so we amortize at least
|
|
* part of the start up time by enabling 32k XTAL early.
|
|
* App startup code will wait until the oscillator has started up.
|
|
*/
|
|
#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
|
|
if (!rtc_clk_32k_enabled()) {
|
|
rtc_clk_32k_bootstrap(CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES);
|
|
}
|
|
#endif
|
|
}
|