49848eaed5
When SD card is removed during transaction, SDMMC peripheral can report a range of errors, such as timeouts, CRC errors, start/end bit errors. Under normal conditions (card is inserted), SDMMC peripheral also generates command done or data done interrupts. When the card is removed, such interrupts may not be always generated. This change fixes handling of timeout interrupts and SBE interrupts. It also adds a one second timeout into the event processing loop. This timeout allows applications to recover in cases when the SDMMC peripheral doesn’t generate command/data done event on card removal.
483 lines
14 KiB
C
483 lines
14 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdbool.h>
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#include <stddef.h>
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#include <sys/param.h>
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#include "esp_log.h"
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#include "esp_intr_alloc.h"
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#include "soc/sdmmc_struct.h"
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#include "soc/sdmmc_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "rom/gpio.h"
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#include "driver/gpio.h"
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#include "driver/sdmmc_host.h"
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#include "sdmmc_private.h"
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#define SDMMC_EVENT_QUEUE_LENGTH 32
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typedef struct {
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uint32_t clk;
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uint32_t cmd;
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uint32_t d0;
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uint32_t d1;
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uint32_t d2;
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uint32_t d3;
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uint32_t d4;
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uint32_t d5;
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uint32_t d6;
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uint32_t d7;
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uint8_t card_detect;
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uint8_t write_protect;
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uint8_t width;
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} sdmmc_slot_info_t;
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static void sdmmc_isr(void* arg);
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static void sdmmc_host_dma_init();
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static const sdmmc_slot_info_t s_slot_info[2] = {
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{
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.clk = PERIPHS_IO_MUX_SD_CLK_U,
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.cmd = PERIPHS_IO_MUX_SD_CMD_U,
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.d0 = PERIPHS_IO_MUX_SD_DATA0_U,
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.d1 = PERIPHS_IO_MUX_SD_DATA1_U,
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.d2 = PERIPHS_IO_MUX_SD_DATA2_U,
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.d3 = PERIPHS_IO_MUX_SD_DATA3_U,
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.d4 = PERIPHS_IO_MUX_GPIO16_U,
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.d5 = PERIPHS_IO_MUX_GPIO17_U,
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.d6 = PERIPHS_IO_MUX_GPIO5_U,
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.d7 = PERIPHS_IO_MUX_GPIO18_U,
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.card_detect = HOST_CARD_DETECT_N_1_IDX,
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.write_protect = HOST_CARD_WRITE_PRT_1_IDX,
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.width = 8
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},
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{
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.clk = PERIPHS_IO_MUX_MTMS_U,
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.cmd = PERIPHS_IO_MUX_MTDO_U,
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.d0 = PERIPHS_IO_MUX_GPIO2_U,
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.d1 = PERIPHS_IO_MUX_GPIO4_U,
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.d2 = PERIPHS_IO_MUX_MTDI_U,
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.d3 = PERIPHS_IO_MUX_MTCK_U,
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.card_detect = HOST_CARD_DETECT_N_2_IDX,
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.write_protect = HOST_CARD_WRITE_PRT_2_IDX,
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.width = 4
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}
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};
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static const char* TAG = "sdmmc_periph";
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static intr_handle_t s_intr_handle;
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static QueueHandle_t s_event_queue;
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void sdmmc_host_reset()
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{
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// Set reset bits
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SDMMC.ctrl.controller_reset = 1;
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SDMMC.ctrl.dma_reset = 1;
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SDMMC.ctrl.fifo_reset = 1;
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// Wait for the reset bits to be cleared by hardware
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while (SDMMC.ctrl.controller_reset || SDMMC.ctrl.fifo_reset || SDMMC.ctrl.dma_reset) {
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;
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}
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}
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/* We have two clock divider stages:
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* - one is the clock generator which drives SDMMC peripheral,
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* it can be configured using SDMMC.clock register. It can generate
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* frequencies 160MHz/(N + 1), where 0 < N < 16, I.e. from 10 to 80 MHz.
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* - 4 clock dividers inside SDMMC peripheral, which can divide clock
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* from the first stage by 2 * M, where 0 < M < 255
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* (they can also be bypassed).
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*
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* For cards which aren't UHS-1 or UHS-2 cards, which we don't support,
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* maximum bus frequency in high speed (HS) mode is 50 MHz.
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* Note: for non-UHS-1 cards, HS mode is optional.
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* Default speed (DS) mode is mandatory, it works up to 25 MHz.
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* Whether the card supports HS or not can be determined using TRAN_SPEED
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* field of card's CSD register.
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*
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* 50 MHz can not be obtained exactly, closest we can get is 53 MHz.
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* For now set the first stage divider to generate 40MHz, and then configure
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* the second stage dividers to generate the frequency requested.
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*
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* Of the second stage dividers, div0 is used for card 0, and div1 is used
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* for card 1.
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*/
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static void sdmmc_host_input_clk_enable()
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{
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// Set frequency to 160MHz / (p + 1) = 40MHz, duty cycle (h + 1)/(p + 1) = 1/2
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SDMMC.clock.div_factor_p = 3;
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SDMMC.clock.div_factor_h = 1;
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SDMMC.clock.div_factor_m = 3;
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// Set phases for in/out clocks
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SDMMC.clock.phase_dout = 4;
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SDMMC.clock.phase_din = 4;
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SDMMC.clock.phase_core = 0;
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// Wait for the clock to propagate
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ets_delay_us(10);
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}
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static void sdmmc_host_input_clk_disable()
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{
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SDMMC.clock.val = 0;
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}
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static void sdmmc_host_clock_update_command(int slot)
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{
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// Clock update command (not a real command; just updates CIU registers)
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sdmmc_hw_cmd_t cmd_val = {
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.card_num = slot,
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.update_clk_reg = 1,
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.wait_complete = 1
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};
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bool repeat = true;
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while(repeat) {
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sdmmc_host_start_command(slot, cmd_val, 0);
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while (true) {
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// Sending clock update command to the CIU can generate HLE error.
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// According to the manual, this is okay and we must retry the command.
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if (SDMMC.rintsts.hle) {
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SDMMC.rintsts.hle = 1;
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repeat = true;
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break;
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}
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// When the command is accepted by CIU, start_command bit will be
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// cleared in SDMMC.cmd register.
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if (SDMMC.cmd.start_command == 0) {
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repeat = false;
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break;
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}
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}
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}
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}
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esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz)
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{
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if (!(slot == 0 || slot == 1)) {
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return ESP_ERR_INVALID_ARG;
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}
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const int clk40m = 40000;
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// Disable clock first
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SDMMC.clkena.cclk_enable &= ~BIT(slot);
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sdmmc_host_clock_update_command(slot);
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// Calculate new dividers
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int div = 0;
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if (freq_khz < clk40m) {
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// round up; extra *2 is because clock divider divides by 2*n
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div = (clk40m + freq_khz * 2 - 1) / (freq_khz * 2);
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}
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ESP_LOGD(TAG, "slot=%d div=%d freq=%dkHz", slot, div,
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(div == 0) ? clk40m : clk40m / (2 * div));
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// Program CLKDIV and CLKSRC, send them to the CIU
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switch(slot) {
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case 0:
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SDMMC.clksrc.card0 = 0;
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SDMMC.clkdiv.div0 = div;
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break;
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case 1:
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SDMMC.clksrc.card1 = 1;
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SDMMC.clkdiv.div1 = div;
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break;
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}
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sdmmc_host_clock_update_command(slot);
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// Re-enable clocks
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SDMMC.clkena.cclk_enable |= BIT(slot);
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SDMMC.clkena.cclk_low_power |= BIT(slot);
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sdmmc_host_clock_update_command(slot);
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// set data timeout
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const uint32_t data_timeout_ms = 100;
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uint32_t data_timeout_cycles = data_timeout_ms * freq_khz;
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const uint32_t data_timeout_cycles_max = 0xffffff;
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if (data_timeout_cycles > data_timeout_cycles_max) {
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data_timeout_cycles = data_timeout_cycles_max;
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}
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SDMMC.tmout.data = data_timeout_cycles;
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// always set response timeout to highest value, it's small enough anyway
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SDMMC.tmout.response = 255;
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return ESP_OK;
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}
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esp_err_t sdmmc_host_start_command(int slot, sdmmc_hw_cmd_t cmd, uint32_t arg) {
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if (!(slot == 0 || slot == 1)) {
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return ESP_ERR_INVALID_ARG;
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}
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while (SDMMC.cmd.start_command == 1) {
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;
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}
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SDMMC.cmdarg = arg;
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cmd.card_num = slot;
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cmd.start_command = 1;
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SDMMC.cmd = cmd;
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return ESP_OK;
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}
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esp_err_t sdmmc_host_init()
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{
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if (s_intr_handle) {
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return ESP_ERR_INVALID_STATE;
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}
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// Enable clock to peripheral
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sdmmc_host_input_clk_enable();
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// Reset
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sdmmc_host_reset();
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ESP_LOGD(TAG, "peripheral version %x, hardware config %08x", SDMMC.verid, SDMMC.hcon);
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// Clear interrupt status and set interrupt mask to known state
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SDMMC.rintsts.val = 0xffffffff;
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SDMMC.intmask.val = 0;
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SDMMC.ctrl.int_enable = 0;
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// Allocate event queue
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s_event_queue = xQueueCreate(SDMMC_EVENT_QUEUE_LENGTH, sizeof(sdmmc_event_t));
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if (!s_event_queue) {
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return ESP_ERR_NO_MEM;
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}
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// Attach interrupt handler
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esp_err_t ret = esp_intr_alloc(ETS_SDIO_HOST_INTR_SOURCE, 0, &sdmmc_isr, s_event_queue, &s_intr_handle);
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if (ret != ESP_OK) {
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vQueueDelete(s_event_queue);
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s_event_queue = NULL;
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return ret;
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}
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// Enable interrupts
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SDMMC.intmask.val =
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SDMMC_INTMASK_CD |
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SDMMC_INTMASK_CMD_DONE |
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SDMMC_INTMASK_DATA_OVER |
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SDMMC_INTMASK_RCRC | SDMMC_INTMASK_DCRC |
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SDMMC_INTMASK_RTO | SDMMC_INTMASK_DTO | SDMMC_INTMASK_HTO |
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SDMMC_INTMASK_SBE | SDMMC_INTMASK_EBE |
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SDMMC_INTMASK_RESP_ERR | SDMMC_INTMASK_HLE;
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SDMMC.ctrl.int_enable = 1;
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// Enable DMA
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sdmmc_host_dma_init();
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// Initialize transaction handler
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ret = sdmmc_host_transaction_handler_init();
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if (ret != ESP_OK) {
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vQueueDelete(s_event_queue);
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s_event_queue = NULL;
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esp_intr_free(s_intr_handle);
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s_intr_handle = NULL;
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return ret;
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}
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return ESP_OK;
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}
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static inline void configure_pin(uint32_t io_mux_reg)
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{
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const int sdmmc_func = 3;
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const int drive_strength = 3;
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PIN_INPUT_ENABLE(io_mux_reg);
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PIN_FUNC_SELECT(io_mux_reg, sdmmc_func);
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PIN_SET_DRV(io_mux_reg, drive_strength);
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}
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esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t* slot_config)
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{
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if (!s_intr_handle) {
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return ESP_ERR_INVALID_STATE;
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}
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if (!(slot == 0 || slot == 1)) {
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return ESP_ERR_INVALID_ARG;
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}
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if (slot_config == NULL) {
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return ESP_ERR_INVALID_ARG;
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}
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int gpio_cd = slot_config->gpio_cd;
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int gpio_wp = slot_config->gpio_wp;
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uint8_t slot_width = slot_config->width;
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// Configure pins
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const sdmmc_slot_info_t* pslot = &s_slot_info[slot];
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if (slot_width == SDMMC_SLOT_WIDTH_DEFAULT) {
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slot_width = pslot->width;
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}
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else if (slot_width > pslot->width) {
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return ESP_ERR_INVALID_ARG;
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}
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configure_pin(pslot->clk);
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configure_pin(pslot->cmd);
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configure_pin(pslot->d0);
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if (slot_width >= 4) {
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configure_pin(pslot->d1);
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configure_pin(pslot->d2);
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configure_pin(pslot->d3);
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if (slot_width == 8) {
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configure_pin(pslot->d4);
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configure_pin(pslot->d5);
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configure_pin(pslot->d6);
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configure_pin(pslot->d7);
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}
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}
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if (gpio_cd != -1) {
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gpio_set_direction(gpio_cd, GPIO_MODE_INPUT);
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gpio_matrix_in(gpio_cd, pslot->card_detect, 0);
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}
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if (gpio_wp != -1) {
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gpio_set_direction(gpio_wp, GPIO_MODE_INPUT);
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gpio_matrix_in(gpio_wp, pslot->write_protect, 0);
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}
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// By default, set probing frequency (400kHz) and 1-bit bus
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esp_err_t ret = sdmmc_host_set_card_clk(slot, 400);
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if (ret != ESP_OK) {
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return ret;
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}
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ret = sdmmc_host_set_bus_width(slot, 1);
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if (ret != ESP_OK) {
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return ret;
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}
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return ESP_OK;
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}
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esp_err_t sdmmc_host_deinit()
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{
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if (!s_intr_handle) {
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return ESP_ERR_INVALID_STATE;
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}
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esp_intr_free(s_intr_handle);
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s_intr_handle = NULL;
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vQueueDelete(s_event_queue);
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s_event_queue = NULL;
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sdmmc_host_input_clk_disable();
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sdmmc_host_transaction_handler_deinit();
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return ESP_OK;
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}
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esp_err_t sdmmc_host_wait_for_event(int tick_count, sdmmc_event_t* out_event)
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{
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if (!out_event) {
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return ESP_ERR_INVALID_ARG;
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}
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if (!s_event_queue) {
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return ESP_ERR_INVALID_STATE;
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}
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int ret = xQueueReceive(s_event_queue, out_event, tick_count);
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if (ret == pdFALSE) {
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return ESP_ERR_TIMEOUT;
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}
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return ESP_OK;
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}
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esp_err_t sdmmc_host_set_bus_width(int slot, size_t width)
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{
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if (!(slot == 0 || slot == 1)) {
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return ESP_ERR_INVALID_ARG;
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}
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if (s_slot_info[slot].width < width) {
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return ESP_ERR_INVALID_ARG;
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}
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const uint16_t mask = BIT(slot);
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if (width == 1) {
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SDMMC.ctype.card_width_8 &= ~mask;
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SDMMC.ctype.card_width &= ~mask;
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} else if (width == 4) {
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SDMMC.ctype.card_width_8 &= ~mask;
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SDMMC.ctype.card_width |= mask;
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} else if (width == 8){
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SDMMC.ctype.card_width_8 |= mask;
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} else {
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return ESP_ERR_INVALID_ARG;
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}
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ESP_LOGD(TAG, "slot=%d width=%d", slot, width);
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return ESP_OK;
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}
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static void sdmmc_host_dma_init()
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{
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SDMMC.ctrl.dma_enable = 1;
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SDMMC.bmod.val = 0;
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SDMMC.bmod.sw_reset = 1;
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SDMMC.idinten.ni = 1;
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SDMMC.idinten.ri = 1;
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SDMMC.idinten.ti = 1;
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}
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void sdmmc_host_dma_stop()
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{
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SDMMC.ctrl.use_internal_dma = 0;
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SDMMC.ctrl.dma_reset = 1;
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SDMMC.bmod.fb = 0;
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SDMMC.bmod.enable = 0;
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}
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void sdmmc_host_dma_prepare(sdmmc_desc_t* desc, size_t block_size, size_t data_size)
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{
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// Set size of data and DMA descriptor pointer
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SDMMC.bytcnt = data_size;
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SDMMC.blksiz = block_size;
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SDMMC.dbaddr = desc;
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// Enable everything needed to use DMA
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SDMMC.ctrl.dma_enable = 1;
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SDMMC.ctrl.use_internal_dma = 1;
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SDMMC.bmod.enable = 1;
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SDMMC.bmod.fb = 1;
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sdmmc_host_dma_resume();
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}
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void sdmmc_host_dma_resume()
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{
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SDMMC.pldmnd = 1;
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}
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/**
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* @brief SDMMC interrupt handler
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*
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* Ignoring SDIO and streaming read/writes for now (and considering just SD memory cards),
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* all communication is driven by the master, and the hardware handles things like stop
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* commands automatically. So the interrupt handler doesn't need to do much, we just push
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* interrupt status into a queue, clear interrupt flags, and let the task currently doing
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* communication figure out what to do next.
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*
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* Card detect interrupts pose a small issue though, because if a card is plugged in and
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* out a few times, while there is no task to process the events, event queue can become
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* full and some card detect events may be dropped. We ignore this problem for now, since
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* the there are no other interesting events which can get lost due to this.
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*/
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static void sdmmc_isr(void* arg) {
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QueueHandle_t queue = (QueueHandle_t) arg;
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sdmmc_event_t event;
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uint32_t pending = SDMMC.mintsts.val;
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SDMMC.rintsts.val = pending;
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event.sdmmc_status = pending;
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uint32_t dma_pending = SDMMC.idsts.val;
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SDMMC.idsts.val = dma_pending;
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event.dma_status = dma_pending & 0x1f;
|
|
|
|
int higher_priority_task_awoken = pdFALSE;
|
|
xQueueSendFromISR(queue, &event, &higher_priority_task_awoken);
|
|
if (higher_priority_task_awoken == pdTRUE) {
|
|
portYIELD_FROM_ISR();
|
|
}
|
|
}
|
|
|