849 lines
36 KiB
C
849 lines
36 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/ets_sys.h"
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#include "esp32/rom/gpio.h"
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#include "esp32/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/ets_sys.h"
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#include "esp32s2beta/rom/gpio.h"
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#include "esp32s2beta/rom/spi_flash.h"
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#endif
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#include "soc/spi_periph.h"
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#define SPI_IDX 1
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#define OTH_IDX 0
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extern esp_rom_spiflash_chip_t g_rom_spiflash_chip;
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esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi)
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{
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uint32_t status;
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#if CONFIG_IDF_TARGET_ESP32
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//wait for spi control ready
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while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) {
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}
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while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) {
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}
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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while ((REG_READ(SPI_MEM_FSM_REG(1)) & SPI_MEM_ST)) {
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}
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while ((REG_READ(SPI_MEM_FSM_REG(0)) & SPI_MEM_ST)) {
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}
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#endif
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//wait for flash status ready
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if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_status(spi, &status)) {
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return ESP_ROM_SPIFLASH_RESULT_ERR;
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}
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return ESP_ROM_SPIFLASH_RESULT_OK;
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}
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/* Modified version of esp_rom_spiflash_unlock() that replaces version in ROM.
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This works around a bug where esp_rom_spiflash_unlock sometimes reads the wrong
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high status byte (RDSR2 result) and then copies it back to the
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flash status, which can cause the CMP bit or Status Register
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Protect bit to become set.
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Like other ROM SPI functions, this function is not designed to be
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called directly from an RTOS environment without taking precautions
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about interrupts, CPU coordination, flash mapping. However some of
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the functions in esp_spi_flash.c call it.
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*/
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esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void)
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{
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uint32_t status;
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esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
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if (esp_rom_spiflash_read_statushigh(&g_rom_spiflash_chip, &status) != ESP_ROM_SPIFLASH_RESULT_OK) {
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return ESP_ROM_SPIFLASH_RESULT_ERR;
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}
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/* Clear all bits except QIE, if it is set.
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(This is different from ROM esp_rom_spiflash_unlock, which keeps all bits as-is.)
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*/
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status &= ESP_ROM_SPIFLASH_QE;
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esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
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#if CONFIG_IDF_TARGET_ESP32
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REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WREN);
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while (REG_READ(SPI_CMD_REG(SPI_IDX)) != 0) {
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}
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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REG_WRITE(SPI_MEM_CMD_REG(SPI_IDX), SPI_MEM_FLASH_WREN);
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while (REG_READ(SPI_MEM_CMD_REG(SPI_IDX)) != 0) {
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}
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#endif
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esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
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#if CONFIG_IDF_TARGET_ESP32
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SET_PERI_REG_MASK(SPI_CTRL_REG(SPI_IDX), SPI_WRSR_2B);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(SPI_IDX), SPI_MEM_WRSR_2B);
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#endif
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if (esp_rom_spiflash_write_status(&g_rom_spiflash_chip, status) != ESP_ROM_SPIFLASH_RESULT_OK) {
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return ESP_ROM_SPIFLASH_RESULT_ERR;
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}
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return ESP_ROM_SPIFLASH_RESULT_OK;
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}
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#if CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t *spi);
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//only support spi1
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static esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip_internal(esp_rom_spiflash_chip_t *spi)
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{
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esp_rom_spiflash_wait_idle(spi);
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// Chip erase.
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#if CONFIG_IDF_TARGET_ESP32
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_CE);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_MEM_FLASH_CE);
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#endif
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while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
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// check erase is finished.
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esp_rom_spiflash_wait_idle(spi);
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return ESP_ROM_SPIFLASH_RESULT_OK;
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}
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//only support spi1
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static esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector_internal(esp_rom_spiflash_chip_t *spi, uint32_t addr)
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{
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//check if addr is 4k alignment
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if (0 != (addr & 0xfff)) {
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return ESP_ROM_SPIFLASH_RESULT_ERR;
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}
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esp_rom_spiflash_wait_idle(spi);
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// sector erase 4Kbytes erase is sector erase.
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff);
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#if CONFIG_IDF_TARGET_ESP32
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_SE);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_MEM_FLASH_SE);
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#endif
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while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
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esp_rom_spiflash_wait_idle(spi);
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return ESP_ROM_SPIFLASH_RESULT_OK;
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}
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//only support spi1
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static esp_rom_spiflash_result_t esp_rom_spiflash_erase_block_internal(esp_rom_spiflash_chip_t *spi, uint32_t addr)
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{
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esp_rom_spiflash_wait_idle(spi);
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// sector erase 4Kbytes erase is sector erase.
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff);
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#if CONFIG_IDF_TARGET_ESP32
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_BE);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_MEM_FLASH_BE);
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#endif
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while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
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esp_rom_spiflash_wait_idle(spi);
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return ESP_ROM_SPIFLASH_RESULT_OK;
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}
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//only support spi1
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static esp_rom_spiflash_result_t esp_rom_spiflash_program_page_internal(esp_rom_spiflash_chip_t *spi, uint32_t spi_addr,
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uint32_t *addr_source, int32_t byte_length)
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{
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uint32_t temp_addr;
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int32_t temp_bl;
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uint8_t i;
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uint8_t remain_word_num;
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//check 4byte alignment
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if (0 != (byte_length & 0x3)) {
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return ESP_ROM_SPIFLASH_RESULT_ERR;
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}
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//check if write in one page
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if ((spi->page_size) < ((spi_addr % (spi->page_size)) + byte_length)) {
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return ESP_ROM_SPIFLASH_RESULT_ERR;
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}
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esp_rom_spiflash_wait_idle(spi);
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temp_addr = spi_addr;
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temp_bl = byte_length;
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while (temp_bl > 0 ) {
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if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(spi)) {
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return ESP_ROM_SPIFLASH_RESULT_ERR;
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}
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if ( temp_bl >= ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM ) {
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | ( ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM << ESP_ROM_SPIFLASH_BYTES_LEN )); // 32 byte a block
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for (i = 0; i < (ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM >> 2); i++) {
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++);
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}
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temp_bl = temp_bl - 32;
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temp_addr = temp_addr + 32;
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} else {
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | (temp_bl << ESP_ROM_SPIFLASH_BYTES_LEN ));
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remain_word_num = (0 == (temp_bl & 0x3)) ? (temp_bl >> 2) : (temp_bl >> 2) + 1;
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for (i = 0; i < remain_word_num; i++) {
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++);
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temp_bl = temp_bl - 4;
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}
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temp_bl = 0;
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}
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#if CONFIG_IDF_TARGET_ESP32
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_PP);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_MEM_FLASH_PP);
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#endif
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while ( READ_PERI_REG(PERIPHS_SPI_FLASH_CMD ) != 0 );
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esp_rom_spiflash_wait_idle(spi);
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}
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return ESP_ROM_SPIFLASH_RESULT_OK;
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}
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//only support spi1
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static esp_rom_spiflash_result_t esp_rom_spiflash_read_data(esp_rom_spiflash_chip_t *spi, uint32_t flash_addr,
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uint32_t *addr_dest, int32_t byte_length)
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{
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uint32_t temp_addr;
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int32_t temp_length;
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uint8_t i;
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uint8_t remain_word_num;
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//address range check
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if ((flash_addr + byte_length) > (spi->chip_size)) {
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return ESP_ROM_SPIFLASH_RESULT_ERR;
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}
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temp_addr = flash_addr;
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temp_length = byte_length;
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esp_rom_spiflash_wait_idle(spi);
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while (temp_length > 0) {
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if (temp_length >= ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM) {
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//WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << ESP_ROM_SPIFLASH_BYTES_LEN));
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#if CONFIG_IDF_TARGET_ESP32
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REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_DBITLEN_S);
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);
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REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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REG_WRITE(SPI_MEM_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_MEM_USR_MISO_DBITLEN_S);
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);
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REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_MEM_USR);
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#endif
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while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0);
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for (i = 0; i < (ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM >> 2); i++) {
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*addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4);
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}
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temp_length = temp_length - ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM;
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temp_addr = temp_addr + ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM;
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} else {
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//WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(temp_length << ESP_ROM_SPIFLASH_BYTES_LEN ));
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);
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#if CONFIG_IDF_TARGET_ESP32
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REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_DBITLEN_S);
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REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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REG_WRITE(SPI_MEM_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_MEM_USR_MISO_DBITLEN_S);
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REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_MEM_USR);
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#endif
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while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0);
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remain_word_num = (0 == (temp_length & 0x3)) ? (temp_length >> 2) : (temp_length >> 2) + 1;
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for (i = 0; i < remain_word_num; i++) {
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*addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4);
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}
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temp_length = 0;
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}
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}
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return ESP_ROM_SPIFLASH_RESULT_OK;
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}
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esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status)
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{
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uint32_t status_value = ESP_ROM_SPIFLASH_BUSY_FLAG;
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if (g_rom_spiflash_dummy_len_plus[1] == 0) {
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while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) {
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, 0); // clear regisrter
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#if CONFIG_IDF_TARGET_ESP32
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_RDSR);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_MEM_FLASH_RDSR);
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#endif
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while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
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status_value = READ_PERI_REG(PERIPHS_SPI_FLASH_STATUS) & (spi->status_mask);
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}
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} else {
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while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) {
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esp_rom_spiflash_read_user_cmd(&status_value, 0x05);
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}
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}
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*status = status_value;
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return ESP_ROM_SPIFLASH_RESULT_OK;
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}
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esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status)
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{
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esp_rom_spiflash_result_t ret;
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esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
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ret = esp_rom_spiflash_read_user_cmd(status, 0x35);
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*status = *status << 8;
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return ret;
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}
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esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value)
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{
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esp_rom_spiflash_wait_idle(spi);
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// update status value by status_value
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, status_value); // write status regisrter
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#if CONFIG_IDF_TARGET_ESP32
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WRSR);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_MEM_FLASH_WRSR);
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#endif
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while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
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esp_rom_spiflash_wait_idle(spi);
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return ESP_ROM_SPIFLASH_RESULT_OK;
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}
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static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t *spi)
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{
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uint32_t flash_status = 0;
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esp_rom_spiflash_wait_idle(spi);
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//enable write
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#if CONFIG_IDF_TARGET_ESP32
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WREN); // enable write operation
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_MEM_FLASH_WREN); // enable write operation
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#endif
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while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
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// make sure the flash is ready for writing
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while (ESP_ROM_SPIFLASH_WRENABLE_FLAG != (flash_status & ESP_ROM_SPIFLASH_WRENABLE_FLAG)) {
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esp_rom_spiflash_read_status(spi, &flash_status);
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}
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return ESP_ROM_SPIFLASH_RESULT_OK;
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}
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static void spi_cache_mode_switch(uint32_t modebit)
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{
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#if CONFIG_IDF_TARGET_ESP32
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if ((modebit & SPI_FREAD_QIO) && (modebit & SPI_FASTRD_MODE)) {
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REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI);
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REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
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REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_QIO_ADDR_BITSLEN);
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REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
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REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xEB);
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} else if (modebit & SPI_FASTRD_MODE) {
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REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI);
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REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
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REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_FAST_ADDR_BITSLEN);
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if ((modebit & SPI_FREAD_QUAD)) {
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REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x6B);
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REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
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} else if ((modebit & SPI_FREAD_DIO)) {
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REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_DIO_ADDR_BITSLEN);
|
|
REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_DIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
|
|
REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xBB);
|
|
} else if ((modebit & SPI_FREAD_DUAL)) {
|
|
REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
|
|
REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x3B);
|
|
} else {
|
|
REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
|
|
REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x0B);
|
|
}
|
|
} else {
|
|
REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI);
|
|
if (g_rom_spiflash_dummy_len_plus[0] == 0) {
|
|
REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_DUMMY);
|
|
} else {
|
|
REG_SET_BIT(SPI_USER_REG(0), SPI_USR_DUMMY);
|
|
REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[0] - 1);
|
|
}
|
|
REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_ADDR);
|
|
REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_SIO_ADDR_BITSLEN);
|
|
REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x03);
|
|
}
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
if ((modebit & SPI_MEM_FREAD_QIO) && (modebit & SPI_MEM_FASTRD_MODE)) {
|
|
REG_CLR_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_MOSI);
|
|
REG_SET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_MISO | SPI_MEM_USR_DUMMY | SPI_MEM_USR_ADDR);
|
|
REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_ADDR_BITLEN, SPI0_R_QIO_ADDR_BITSLEN);
|
|
REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, SPI0_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
|
|
REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, 0xEB);
|
|
} else if (modebit & SPI_MEM_FASTRD_MODE) {
|
|
REG_CLR_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_MOSI);
|
|
REG_SET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_MISO | SPI_MEM_USR_DUMMY | SPI_MEM_USR_ADDR);
|
|
REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_ADDR_BITLEN, SPI0_R_FAST_ADDR_BITSLEN);
|
|
if ((modebit & SPI_MEM_FREAD_QUAD)) {
|
|
REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, 0x6B);
|
|
REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
|
|
} else if ((modebit & SPI_MEM_FREAD_DIO)) {
|
|
REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, SPI0_R_DIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
|
|
REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, 0xBB);
|
|
} else if ((modebit & SPI_MEM_FREAD_DUAL)) {
|
|
REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
|
|
REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, 0x3B);
|
|
} else{
|
|
REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
|
|
REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, 0x0B);
|
|
}
|
|
} else {
|
|
REG_CLR_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_MOSI);
|
|
if (g_rom_spiflash_dummy_len_plus[0] == 0) {
|
|
REG_CLR_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY);
|
|
} else {
|
|
REG_SET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY);
|
|
REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[0] - 1);
|
|
}
|
|
REG_SET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_MISO | SPI_MEM_USR_ADDR);
|
|
REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_ADDR_BITLEN, SPI0_R_SIO_ADDR_BITSLEN);
|
|
REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, 0x03);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
esp_rom_spiflash_result_t esp_rom_spiflash_lock(void)
|
|
{
|
|
uint32_t status;
|
|
|
|
//read QE bit, not write if not QE
|
|
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_statushigh(&g_rom_spiflash_chip, &status)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
//enable 2 byte status writing
|
|
SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN);
|
|
|
|
if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_write_status(&g_rom_spiflash_chip, status | ESP_ROM_SPIFLASH_WR_PROTECT)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
return ESP_ROM_SPIFLASH_RESULT_OK;
|
|
}
|
|
|
|
|
|
esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode)
|
|
{
|
|
uint32_t modebit;
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) {
|
|
}
|
|
while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) {
|
|
}
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
while ((REG_READ(SPI_MEM_FSM_REG(1)) & SPI_MEM_ST)) {
|
|
}
|
|
while ((REG_READ(SPI_MEM_FSM_REG(0)) & SPI_MEM_ST)) {
|
|
}
|
|
#endif
|
|
//clear old mode bit
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_FREAD_QIO | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_DUAL | SPI_FASTRD_MODE);
|
|
CLEAR_PERI_REG_MASK(SPI_CTRL_REG(0), SPI_FREAD_QIO | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_DUAL | SPI_FASTRD_MODE);
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE);
|
|
CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE);
|
|
#endif
|
|
//configure read mode
|
|
switch (mode) {
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
case ESP_ROM_SPIFLASH_QIO_MODE : modebit = SPI_FREAD_QIO | SPI_FASTRD_MODE; break;
|
|
case ESP_ROM_SPIFLASH_QOUT_MODE : modebit = SPI_FREAD_QUAD | SPI_FASTRD_MODE; break;
|
|
case ESP_ROM_SPIFLASH_DIO_MODE : modebit = SPI_FREAD_DIO | SPI_FASTRD_MODE; break;
|
|
case ESP_ROM_SPIFLASH_DOUT_MODE : modebit = SPI_FREAD_DUAL | SPI_FASTRD_MODE; break;
|
|
case ESP_ROM_SPIFLASH_FASTRD_MODE: modebit = SPI_FASTRD_MODE; break;
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
case ESP_ROM_SPIFLASH_QIO_MODE : modebit = SPI_MEM_FREAD_QIO | SPI_MEM_FASTRD_MODE; break;
|
|
case ESP_ROM_SPIFLASH_QOUT_MODE : modebit = SPI_MEM_FREAD_QUAD | SPI_MEM_FASTRD_MODE; break;
|
|
case ESP_ROM_SPIFLASH_DIO_MODE : modebit = SPI_MEM_FREAD_DIO | SPI_MEM_FASTRD_MODE; break;
|
|
case ESP_ROM_SPIFLASH_DOUT_MODE : modebit = SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE; break;
|
|
case ESP_ROM_SPIFLASH_FASTRD_MODE: modebit = SPI_MEM_FASTRD_MODE; break;
|
|
#endif
|
|
case ESP_ROM_SPIFLASH_SLOWRD_MODE: modebit = 0; break;
|
|
default : modebit = 0;
|
|
}
|
|
|
|
SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, modebit);
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
SET_PERI_REG_MASK(SPI_CTRL_REG(0), modebit);
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(0), modebit);
|
|
#endif
|
|
spi_cache_mode_switch(modebit);
|
|
|
|
return ESP_ROM_SPIFLASH_RESULT_OK;
|
|
}
|
|
|
|
esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void)
|
|
{
|
|
if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_chip_internal(&g_rom_spiflash_chip)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
return ESP_ROM_SPIFLASH_RESULT_OK;
|
|
}
|
|
|
|
esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num)
|
|
{
|
|
// flash write is always 1 line currently
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_MEM_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
|
|
#endif
|
|
//check program size
|
|
if (block_num >= ((g_rom_spiflash_chip.chip_size) / (g_rom_spiflash_chip.block_size))) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_block_internal(&g_rom_spiflash_chip, block_num * (g_rom_spiflash_chip.block_size))) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
return ESP_ROM_SPIFLASH_RESULT_OK;
|
|
}
|
|
|
|
esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num)
|
|
{
|
|
// flash write is always 1 line currently
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_MEM_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
|
|
#endif
|
|
//check program size
|
|
if (sector_num >= ((g_rom_spiflash_chip.chip_size) / (g_rom_spiflash_chip.sector_size))) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector_internal(&g_rom_spiflash_chip, sector_num * (g_rom_spiflash_chip.sector_size))) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
return ESP_ROM_SPIFLASH_RESULT_OK;
|
|
}
|
|
|
|
esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t target, const uint32_t *src_addr, int32_t len)
|
|
{
|
|
uint32_t page_size;
|
|
uint32_t pgm_len, pgm_num;
|
|
uint8_t i;
|
|
|
|
// flash write is always 1 line currently
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_MEM_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
|
|
#endif
|
|
//check program size
|
|
if ( (target + len) > (g_rom_spiflash_chip.chip_size)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
page_size = g_rom_spiflash_chip.page_size;
|
|
pgm_len = page_size - (target % page_size);
|
|
if (len < pgm_len) {
|
|
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
|
|
target, (uint32_t *)src_addr, len)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
} else {
|
|
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
|
|
target, (uint32_t *)src_addr, pgm_len)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
//whole page program
|
|
pgm_num = (len - pgm_len) / page_size;
|
|
for (i = 0; i < pgm_num; i++) {
|
|
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
|
|
target + pgm_len, (uint32_t *)src_addr + (pgm_len >> 2), page_size)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
pgm_len += page_size;
|
|
}
|
|
|
|
//remain parts to program
|
|
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
|
|
target + pgm_len, (uint32_t *)src_addr + (pgm_len >> 2), len - pgm_len)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
}
|
|
return ESP_ROM_SPIFLASH_RESULT_OK;
|
|
}
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len)
|
|
{
|
|
esp_rom_spiflash_result_t ret = ESP_ROM_SPIFLASH_RESULT_OK;
|
|
uint32_t i;
|
|
|
|
if ((flash_addr & 0x1f) || (len & 0x1f)) { //check 32 byte alignment
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
esp_rom_spiflash_write_encrypted_enable();
|
|
|
|
for (i = 0; i < (len >> 5); i++) {
|
|
if ((ret = esp_rom_spiflash_prepare_encrypted_data(flash_addr + (i << 5), data + (i << 3))) != ESP_ROM_SPIFLASH_RESULT_OK) {
|
|
break;
|
|
}
|
|
|
|
if ((ret = esp_rom_spiflash_write(flash_addr + (i << 5), data, 32)) != ESP_ROM_SPIFLASH_RESULT_OK) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
esp_rom_spiflash_write_encrypted_disable();
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t target, uint32_t *dest_addr, int32_t len)
|
|
{
|
|
// QIO or SIO, non-QIO regard as SIO
|
|
uint32_t modebit;
|
|
modebit = READ_PERI_REG(PERIPHS_SPI_FLASH_CTRL);
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
if ((modebit & SPI_FREAD_QIO) && (modebit & SPI_FASTRD_MODE)) {
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
|
|
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_QIO_ADDR_BITSLEN);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, SPI1_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]);
|
|
//REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0xEB);
|
|
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xEB);
|
|
} else if (modebit & SPI_FASTRD_MODE) {
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
|
|
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR);
|
|
if (modebit & SPI_FREAD_DIO) {
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
if ((modebit & SPI_MEM_FREAD_QIO) && (modebit & SPI_MEM_FASTRD_MODE)) {
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_MOSI);
|
|
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_MISO | SPI_MEM_USR_DUMMY | SPI_MEM_USR_ADDR);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_MEM_USR_ADDR_BITLEN, SPI1_R_QIO_ADDR_BITSLEN);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_MEM_USR_DUMMY_CYCLELEN, SPI1_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]);
|
|
//REG_SET_FIELD(PERIPHS_SPI_SPI_MEM_H_USRREG2, SPI_USR_COMMAND_VALUE, 0xEB);
|
|
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_MEM_USR_COMMAND_BITLEN_S) | 0xEB);
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} else if (modebit & SPI_MEM_FASTRD_MODE) {
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_MOSI);
|
|
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_MISO | SPI_MEM_USR_ADDR);
|
|
if (modebit & SPI_MEM_FREAD_DIO) {
|
|
#endif
|
|
if (g_rom_spiflash_dummy_len_plus[1] == 0) {
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|
#if CONFIG_IDF_TARGET_ESP32
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN);
|
|
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xBB);
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_MEM_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN);
|
|
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_MEM_USR_COMMAND_BITLEN_S) | 0xBB);
|
|
#endif
|
|
} else {
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0xBB);
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_MEM_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_MEM_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_MEM_USR_COMMAND_VALUE, 0xBB);
|
|
#endif
|
|
}
|
|
} else {
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
if ((modebit & SPI_FREAD_QUAD)) {
|
|
//REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x6B);
|
|
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x6B);
|
|
} else if ((modebit & SPI_FREAD_DUAL)) {
|
|
//REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x3B);
|
|
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x3B);
|
|
} else {
|
|
//REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x0B);
|
|
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x0B);
|
|
}
|
|
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_FAST_ADDR_BITSLEN);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, SPI1_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]);
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
if ((modebit & SPI_MEM_FREAD_QUAD)) {
|
|
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_MEM_USR_COMMAND_BITLEN_S) | 0x6B);
|
|
} else if ((modebit & SPI_MEM_FREAD_DUAL)) {
|
|
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_MEM_USR_COMMAND_BITLEN_S) | 0x3B);
|
|
} else {
|
|
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_MEM_USR_COMMAND_BITLEN_S) | 0x0B);
|
|
}
|
|
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_MEM_USR_ADDR_BITLEN, SPI1_R_FAST_ADDR_BITSLEN);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_MEM_USR_DUMMY_CYCLELEN, SPI1_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]);
|
|
#endif
|
|
}
|
|
} else {
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
|
|
if (g_rom_spiflash_dummy_len_plus[1] == 0) {
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
|
|
} else {
|
|
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1);
|
|
}
|
|
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_SIO_ADDR_BITSLEN);
|
|
//REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x03);
|
|
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x03);
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_MOSI);
|
|
if (g_rom_spiflash_dummy_len_plus[1] == 0) {
|
|
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY);
|
|
} else {
|
|
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_MEM_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1);
|
|
}
|
|
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_MISO | SPI_MEM_USR_ADDR);
|
|
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_MEM_USR_ADDR_BITLEN, SPI1_R_SIO_ADDR_BITSLEN);
|
|
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_MEM_USR_COMMAND_BITLEN_S) | 0x03);
|
|
#endif
|
|
}
|
|
|
|
if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_data(&g_rom_spiflash_chip, target, dest_addr, len)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
return ESP_ROM_SPIFLASH_RESULT_OK;
|
|
}
|
|
|
|
esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len)
|
|
{
|
|
int32_t total_sector_num;
|
|
int32_t head_sector_num;
|
|
uint32_t sector_no;
|
|
uint32_t sector_num_per_block;
|
|
|
|
//set read mode to Fastmode ,not QDIO mode for erase
|
|
//
|
|
// TODO: this is probably a bug as it doesn't re-enable QIO mode, not serious as this
|
|
// function is not used in IDF.
|
|
esp_rom_spiflash_config_readmode(ESP_ROM_SPIFLASH_SLOWRD_MODE);
|
|
|
|
//check if area is oversize of flash
|
|
if ((start_addr + area_len) > g_rom_spiflash_chip.chip_size) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
//start_addr is aligned as sector boundary
|
|
if (0 != (start_addr % g_rom_spiflash_chip.sector_size)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
//Unlock flash to enable erase
|
|
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_unlock(/*&g_rom_spiflash_chip*/)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
|
|
sector_no = start_addr / g_rom_spiflash_chip.sector_size;
|
|
sector_num_per_block = g_rom_spiflash_chip.block_size / g_rom_spiflash_chip.sector_size;
|
|
total_sector_num = (0 == (area_len % g_rom_spiflash_chip.sector_size)) ? area_len / g_rom_spiflash_chip.sector_size :
|
|
1 + (area_len / g_rom_spiflash_chip.sector_size);
|
|
|
|
//check if erase area reach over block boundary
|
|
head_sector_num = sector_num_per_block - (sector_no % sector_num_per_block);
|
|
|
|
head_sector_num = (head_sector_num >= total_sector_num) ? total_sector_num : head_sector_num;
|
|
|
|
//JJJ, BUG of 6.0 erase
|
|
//middle part of area is aligned by blocks
|
|
total_sector_num -= head_sector_num;
|
|
|
|
//head part of area is erased
|
|
while (0 != head_sector_num) {
|
|
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector(sector_no)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
sector_no++;
|
|
head_sector_num--;
|
|
}
|
|
while (total_sector_num > sector_num_per_block) {
|
|
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_block(sector_no / sector_num_per_block)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
sector_no += sector_num_per_block;
|
|
total_sector_num -= sector_num_per_block;
|
|
}
|
|
|
|
//tail part of area burn
|
|
while (0 < total_sector_num) {
|
|
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector(sector_no)) {
|
|
return ESP_ROM_SPIFLASH_RESULT_ERR;
|
|
}
|
|
sector_no++;
|
|
total_sector_num--;
|
|
}
|
|
|
|
return ESP_ROM_SPIFLASH_RESULT_OK;
|
|
}
|
|
|
|
#endif
|