119 lines
3.9 KiB
C
119 lines
3.9 KiB
C
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdbool.h>
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#include <assert.h>
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#include "string.h"
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp32s2beta/rom/gpio.h"
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#include "esp32s2beta/rom/spi_flash.h"
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#include "esp32s2beta/rom/efuse.h"
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#include "soc/gpio_periph.h"
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#include "soc/efuse_reg.h"
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#include "soc/spi_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/spi_caps.h"
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#include "flash_qio_mode.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_common.h"
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#define FLASH_IO_MATRIX_DUMMY_40M 0
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#define FLASH_IO_MATRIX_DUMMY_80M 0
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#define FLASH_IO_DRIVE_GD_WITH_1V8PSRAM 3
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void bootloader_flash_update_id()
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{
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g_rom_flashchip.device_id = bootloader_read_flash_id();
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}
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void IRAM_ATTR bootloader_flash_cs_timing_config()
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{
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SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
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SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_CS_HOLD_TIME_V, 1, SPI_CS_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_CS_SETUP_TIME_V, 0, SPI_CS_SETUP_TIME_S);
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SET_PERI_REG_MASK(SPI_USER_REG(1), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
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SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_CS_HOLD_TIME_V, 1, SPI_CS_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_CS_SETUP_TIME_V, 0, SPI_CS_SETUP_TIME_S);
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}
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void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr)
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{
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uint32_t spi_clk_div = 0;
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switch (pfhdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_80M:
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spi_clk_div = 1;
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break;
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case ESP_IMAGE_SPI_SPEED_40M:
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spi_clk_div = 2;
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break;
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case ESP_IMAGE_SPI_SPEED_26M:
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spi_clk_div = 3;
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break;
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case ESP_IMAGE_SPI_SPEED_20M:
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spi_clk_div = 4;
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break;
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default:
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break;
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}
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esp_rom_spiflash_config_clk(spi_clk_div, 0);
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}
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void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
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{
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}
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void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
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{
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int spi_cache_dummy = 0;
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int drv = 2;
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switch (pfhdr->spi_mode) {
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case ESP_IMAGE_SPI_MODE_QIO:
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spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
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break;
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case ESP_IMAGE_SPI_MODE_DIO:
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; //qio 3
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break;
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case ESP_IMAGE_SPI_MODE_QOUT:
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case ESP_IMAGE_SPI_MODE_DOUT:
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default:
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
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break;
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}
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/* dummy_len_plus values defined in ROM for SPI flash configuration */
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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switch (pfhdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_80M:
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g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_80M;
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g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_80M;
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SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M,
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SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY
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drv = 3;
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break;
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case ESP_IMAGE_SPI_SPEED_40M:
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g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_40M;
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g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_40M;
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SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M,
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SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY
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break;
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default:
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break;
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}
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bootloader_configure_spi_pins(drv);
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}
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