537 lines
21 KiB
C
537 lines
21 KiB
C
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp_efuse_utility.h"
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#include "soc/efuse_reg.h"
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#include "esp_clk.h"
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#include "esp_log.h"
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#include "assert.h"
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#include "sdkconfig.h"
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#include <sys/param.h>
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static const char *TAG = "efuse";
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#define COUNT_EFUSE_BLOCKS 4 /* The number of blocks. */
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#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */
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#define EFUSE_CONF_WRITE 0x5A5A /* eFuse_pgm_op_ena, force no rd/wr disable. */
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#define EFUSE_CONF_READ 0x5AA5 /* eFuse_read_op_ena, release force. */
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#define EFUSE_CMD_PGM 0x02 /* Command to program. */
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#define EFUSE_CMD_READ 0x01 /* Command to read. */
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// Array for emulate efuse registers.
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#ifdef CONFIG_EFUSE_VIRTUAL
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static uint32_t virt_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK];
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/* Call the update function to seed virtual efuses during initialization */
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__attribute__((constructor)) void esp_efuse_utility_update_virt_blocks();
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#endif
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/**
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* @brief Structure range address by blocks
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*/
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typedef struct {
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uint32_t start;
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uint32_t end;
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} esp_efuse_range_addr_t;
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/*Range addresses to read blocks*/
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static const esp_efuse_range_addr_t range_read_addr_blocks[] = {
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{EFUSE_BLK0_RDATA0_REG, EFUSE_BLK0_RDATA6_REG}, // range address of EFUSE_BLK0
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{EFUSE_BLK1_RDATA0_REG, EFUSE_BLK1_RDATA7_REG}, // range address of EFUSE_BLK1
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{EFUSE_BLK2_RDATA0_REG, EFUSE_BLK2_RDATA7_REG}, // range address of EFUSE_BLK2
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{EFUSE_BLK3_RDATA0_REG, EFUSE_BLK3_RDATA7_REG} // range address of EFUSE_BLK3
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};
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/*Range addresses to write blocks*/
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static const esp_efuse_range_addr_t range_write_addr_blocks[] = {
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{EFUSE_BLK0_WDATA0_REG, EFUSE_BLK0_WDATA6_REG}, // range address of EFUSE_BLK0
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{EFUSE_BLK1_WDATA0_REG, EFUSE_BLK1_WDATA7_REG}, // range address of EFUSE_BLK1
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{EFUSE_BLK2_WDATA0_REG, EFUSE_BLK2_WDATA7_REG}, // range address of EFUSE_BLK2
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{EFUSE_BLK3_WDATA0_REG, EFUSE_BLK3_WDATA7_REG} // range address of EFUSE_BLK3
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};
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static int get_reg_num(int bit_start, int bit_count, int i_reg);
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static int get_starting_bit_num_in_reg(int bit_start, int i_reg);
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static uint32_t get_mask(unsigned int bit_count, unsigned int shift);
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static int get_count_bits_in_reg(int bit_start, int bit_count, int i_reg);
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static void write_reg(esp_efuse_block_t blk, unsigned int num_reg, uint32_t value);
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static uint32_t fill_reg(int bit_start_in_reg, int bit_count_in_reg, uint8_t* blob, int* filled_bits_blob);
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static uint32_t set_cnt_in_reg(int bit_start_in_reg, int bit_count_used_in_reg, uint32_t reg_masked, size_t* cnt);
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static bool check_range_of_bits(esp_efuse_block_t blk, int offset_in_bits, int size_bits);
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// This function processes the field by calling the passed function.
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esp_err_t esp_efuse_utility_process(const esp_efuse_desc_t* field[], void* ptr, size_t ptr_size_bits, efuse_func_proc_t func_proc)
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{
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esp_err_t err = ESP_OK;
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int bits_counter = 0;
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// get and check size.
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int field_len = esp_efuse_get_field_size(field);
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int req_size = (ptr_size_bits == 0) ? field_len : MIN(ptr_size_bits, field_len);
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int i = 0;
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while (err == ESP_OK && req_size > bits_counter && field[i] != NULL) {
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if (check_range_of_bits(field[i]->efuse_block, field[i]->bit_start, field[i]->bit_count) == false) {
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ESP_LOGE(TAG, "Range of data does not match the coding scheme");
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err = ESP_ERR_CODING;
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}
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int i_reg = 0;
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int num_reg;
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while (err == ESP_OK && req_size > bits_counter &&
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(num_reg = get_reg_num(field[i]->bit_start, field[i]->bit_count, i_reg)) != -1) {
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int start_bit = get_starting_bit_num_in_reg(field[i]->bit_start, i_reg);
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int num_bits = get_count_bits_in_reg(field[i]->bit_start, field[i]->bit_count, i_reg);
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if ((bits_counter + num_bits) > req_size) { // Limits the length of the field.
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num_bits = req_size - bits_counter;
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}
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ESP_LOGD(TAG, "In EFUSE_BLK%d__DATA%d_REG is used %d bits starting with %d bit",
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(int)field[i]->efuse_block, num_reg, num_bits, start_bit);
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err = func_proc(num_reg, field[i]->efuse_block, start_bit, num_bits, ptr, &bits_counter);
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++i_reg;
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}
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i++;
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}
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assert(bits_counter <= req_size);
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return err;
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}
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// Read efuse register and write this value to array.
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esp_err_t esp_efuse_utility_fill_buff(unsigned int num_reg, esp_efuse_block_t efuse_block, int bit_start, int bit_count, void* arr_out, int* bits_counter)
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{
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uint8_t* blob = (uint8_t *) arr_out;
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uint32_t reg = esp_efuse_utility_read_reg(efuse_block, num_reg);
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uint64_t reg_of_aligned_bits = (reg >> bit_start) & get_mask(bit_count, 0);
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int shift_bit = (*bits_counter) % 8;
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if (shift_bit != 0) {
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blob[(*bits_counter) / 8] |= (uint8_t)(reg_of_aligned_bits << shift_bit);
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shift_bit = ((8 - shift_bit) < bit_count) ? (8 - shift_bit) : bit_count;
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(*bits_counter) += shift_bit;
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bit_count -= shift_bit;
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}
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int sum_shift = 0;
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while (bit_count > 0) {
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sum_shift += shift_bit;
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blob[(*bits_counter) / 8] |= (uint8_t)(reg_of_aligned_bits >> sum_shift);
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shift_bit = (bit_count > 8) ? 8 : bit_count;
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(*bits_counter) += shift_bit;
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bit_count -= shift_bit;
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};
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return ESP_OK;
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}
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// Count a set bits.
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esp_err_t esp_efuse_utility_count_once(unsigned int num_reg, esp_efuse_block_t efuse_block, int bit_start, int bit_count, void* out_cnt, int* bits_counter)
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{
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uint32_t reg = esp_efuse_utility_read_reg(efuse_block, num_reg);
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*((size_t *)out_cnt) += __builtin_popcount(reg & get_mask(bit_count, bit_start)); // Returns the number of 1-bits in reg.
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*bits_counter += bit_count;
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return ESP_OK;
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}
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// Fill registers from array for writing.
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esp_err_t esp_efuse_utility_write_blob(unsigned int num_reg, esp_efuse_block_t efuse_block, int bit_start, int bit_count, void* arr_in, int* bits_counter)
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{
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uint32_t reg_to_write = fill_reg(bit_start, bit_count, (uint8_t *)arr_in, bits_counter);
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return esp_efuse_utility_write_reg(efuse_block, num_reg, reg_to_write);
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}
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// fill registers with the required number of bits for writing.
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esp_err_t esp_efuse_utility_write_cnt(unsigned int num_reg, esp_efuse_block_t efuse_block, int bit_start, int bit_count, void* cnt, int* bits_counter)
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{
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esp_err_t err = ESP_OK;
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uint32_t reg = esp_efuse_utility_read_reg(efuse_block, num_reg);
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size_t* set_bits = (size_t*)cnt;
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uint32_t mask = get_mask(bit_count, bit_start);
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uint32_t reg_masked_bits = reg & mask;
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if ((reg_masked_bits ^ mask) != 0) {// register has free bits to set them to 1?
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uint32_t reg_to_write = set_cnt_in_reg(bit_start, bit_count, reg_masked_bits, set_bits);
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write_reg(efuse_block, num_reg, reg_to_write);
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}
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*bits_counter += bit_count;
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if ((*set_bits) == 0) {
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err = ESP_OK_EFUSE_CNT;
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}
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return err;
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}
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// Reset efuse write registers
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void esp_efuse_utility_reset(void)
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{
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REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ);
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for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
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for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
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REG_WRITE(addr_wr_block, 0);
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}
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}
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}
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// Burn values written to the efuse write registers
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void esp_efuse_utility_burn_efuses(void)
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{
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#ifdef CONFIG_EFUSE_VIRTUAL
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ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
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for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
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esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(num_block);
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if (scheme == EFUSE_CODING_SCHEME_3_4) {
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uint8_t buf[COUNT_EFUSE_REG_PER_BLOCK * 4] = { 0 };
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int i = 0;
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for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, ++i) {
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*((uint32_t*)buf + i) = REG_READ(addr_wr_block);
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}
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int j = 0;
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uint32_t out_buf[COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
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for (int k = 0; k < 4; ++k, ++j) {
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memcpy((uint8_t*)out_buf + j * 6, &buf[k * 8], 6);
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}
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for (int k = 0; k < COUNT_EFUSE_REG_PER_BLOCK; ++k) {
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REG_WRITE(range_write_addr_blocks[num_block].start + k * 4, out_buf[k]);
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}
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}
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int subblock = 0;
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for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
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virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
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}
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}
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#else
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// Update Efuse timing configuration
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uint32_t apb_freq_mhz = esp_clk_apb_freq() / 1000000;
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uint32_t clk_sel0, clk_sel1, dac_clk_div;
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if (apb_freq_mhz <= 26) {
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clk_sel0 = 250;
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clk_sel1 = 255;
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dac_clk_div = 52;
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} else if (apb_freq_mhz <= 40) {
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clk_sel0 = 160;
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clk_sel1 = 255;
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dac_clk_div = 80;
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} else {
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clk_sel0 = 80;
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clk_sel1 = 128;
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dac_clk_div = 100;
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}
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REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, dac_clk_div);
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REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, clk_sel0);
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REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, clk_sel1);
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// Permanently update values written to the efuse write registers
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REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_WRITE);
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REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_PGM);
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while (REG_READ(EFUSE_CMD_REG) != 0) {};
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REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ);
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REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_READ);
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while (REG_READ(EFUSE_CMD_REG) != 0) {};
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#endif
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esp_efuse_utility_reset();
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}
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// Erase the virt_blocks array.
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void esp_efuse_utility_erase_virt_blocks()
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{
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#ifdef CONFIG_EFUSE_VIRTUAL
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memset(virt_blocks, 0, sizeof(virt_blocks));
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#endif
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}
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// Fills the virt_blocks array by values from efuse_Rdata.
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void esp_efuse_utility_update_virt_blocks()
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{
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#ifdef CONFIG_EFUSE_VIRTUAL
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ESP_LOGI(TAG, "Loading virtual efuse blocks from real efuses");
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for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
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int subblock = 0;
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for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4) {
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virt_blocks[num_block][subblock++] = REG_READ(addr_rd_block);
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}
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ESP_LOGD(TAG, "virt_blocks[%d] is filled by EFUSE_BLOCK%d", num_block, num_block);
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}
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#else
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ESP_LOGI(TAG, "Emulate efuse is disabled");
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#endif
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}
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// Prints efuse values for all registers.
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void esp_efuse_utility_debug_dump_blocks()
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{
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printf("EFUSE_BLKx:\n");
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#ifdef CONFIG_EFUSE_VIRTUAL
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for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
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int num_reg = 0;
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printf("%d) ", num_block);
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for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, num_reg++) {
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printf("0x%08x ", virt_blocks[num_block][num_reg]);
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}
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printf("\n");
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}
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#else
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for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
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printf("%d) ", num_block);
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for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4) {
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printf("0x%08x ", REG_READ(addr_rd_block));
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}
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printf("\n");
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}
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#endif
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printf("\n");
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}
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// returns the number of array elements for placing these bits in an array with the length of each element equal to size_of_base.
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int esp_efuse_utility_get_number_of_items(int bits, int size_of_base)
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{
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return bits / size_of_base + (bits % size_of_base > 0 ? 1 : 0);
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}
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// Writing efuse register with checking of repeated programming of programmed bits.
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esp_err_t esp_efuse_utility_write_reg(esp_efuse_block_t efuse_block, unsigned int num_reg, uint32_t reg_to_write)
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{
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esp_err_t err = ESP_OK;
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uint32_t reg = esp_efuse_utility_read_reg(efuse_block, num_reg);
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if (reg & reg_to_write) {
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ESP_LOGE(TAG, "Repeated programming of programmed bits is strictly forbidden 0x%08x", reg & reg_to_write);
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err = ESP_ERR_EFUSE_REPEATED_PROG;
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} else {
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write_reg(efuse_block, num_reg, reg_to_write);
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}
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return err;
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}
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// Reading efuse register.
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uint32_t esp_efuse_utility_read_reg(esp_efuse_block_t blk, unsigned int num_reg)
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{
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assert(blk >= 0 && blk <= 3);
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if (blk == 0) {
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assert(num_reg <= 6);
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} else {
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assert(num_reg <= 7);
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}
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uint32_t value;
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#ifdef CONFIG_EFUSE_VIRTUAL
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value = virt_blocks[blk][num_reg];
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#else
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value = REG_READ(range_read_addr_blocks[blk].start + num_reg * 4);
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#endif
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return value;
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}
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// Private functions
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// writing efuse register.
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static void write_reg(esp_efuse_block_t blk, unsigned int num_reg, uint32_t value)
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{
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assert(blk >= 0 && blk <= 3);
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if (blk == 0) {
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assert(num_reg <= 6);
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} else {
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assert(num_reg <= 7);
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}
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uint32_t addr_wr_reg = range_write_addr_blocks[blk].start + num_reg * 4;
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uint32_t reg_to_write = REG_READ(addr_wr_reg) | value;
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// The register can be written in parts so we combine the new value with the one already available.
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REG_WRITE(addr_wr_reg, reg_to_write);
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}
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// return mask with required the number of ones with shift.
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static uint32_t get_mask(unsigned int bit_count, unsigned int shift)
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{
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uint32_t mask;
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if (bit_count != 32) {
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mask = (1 << bit_count) - 1;
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} else {
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mask = 0xFFFFFFFF;
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}
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return mask << shift;
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}
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// return the register number in the array. return -1 if all registers for field was selected.
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static int get_reg_num(int bit_start, int bit_count, int i_reg)
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{
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int num_reg = i_reg + bit_start / 32;
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if (num_reg > (bit_start + bit_count - 1) / 32) {
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return -1;
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}
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return num_reg;
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}
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// returns the starting bit number in the register.
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static int get_starting_bit_num_in_reg(int bit_start, int i_reg)
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{
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return (i_reg == 0) ? bit_start % 32 : 0;
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}
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// Returns the number of bits in the register.
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static int get_count_bits_in_reg(int bit_start, int bit_count, int i_reg)
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{
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int ret_count = 0;
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int num_reg = 0;
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int last_used_bit = (bit_start + bit_count - 1);
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for (int num_bit = bit_start; num_bit <= last_used_bit; ++num_bit) {
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++ret_count;
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if ((((num_bit + 1) % 32) == 0) || (num_bit == last_used_bit)) {
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if (i_reg == num_reg++) {
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return ret_count;
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}
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ret_count = 0;
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}
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}
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return 0;
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}
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// fill efuse register from array.
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static uint32_t fill_reg(int bit_start_in_reg, int bit_count_in_reg, uint8_t* blob, int* filled_bits_blob)
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{
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uint32_t reg_to_write = 0;
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uint32_t temp_blob_32;
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int shift_bit = (*filled_bits_blob) % 8;
|
|
if (shift_bit != 0) {
|
|
temp_blob_32 = blob[(*filled_bits_blob) / 8] >> shift_bit;
|
|
shift_bit = ((8 - shift_bit) < bit_count_in_reg) ? (8 - shift_bit) : bit_count_in_reg;
|
|
reg_to_write = temp_blob_32 & get_mask(shift_bit, 0);
|
|
(*filled_bits_blob) += shift_bit;
|
|
bit_count_in_reg -= shift_bit;
|
|
}
|
|
|
|
int shift_reg = shift_bit;
|
|
while (bit_count_in_reg > 0) {
|
|
temp_blob_32 = blob[(*filled_bits_blob) / 8];
|
|
shift_bit = (bit_count_in_reg > 8) ? 8 : bit_count_in_reg;
|
|
reg_to_write |= (temp_blob_32 & get_mask(shift_bit, 0)) << shift_reg;
|
|
(*filled_bits_blob) += shift_bit;
|
|
bit_count_in_reg -= shift_bit;
|
|
shift_reg += 8;
|
|
};
|
|
return reg_to_write << bit_start_in_reg;
|
|
}
|
|
|
|
// sets a required count of bits as "1".
|
|
static uint32_t set_cnt_in_reg(int bit_start_in_reg, int bit_count_used_in_reg, uint32_t reg_masked, size_t* cnt)
|
|
{
|
|
assert((bit_start_in_reg + bit_count_used_in_reg) <= 32);
|
|
uint32_t reg_to_write = 0;
|
|
for (int i = bit_start_in_reg; i < bit_start_in_reg + bit_count_used_in_reg; ++i) {
|
|
if ((reg_masked & (1 << i)) == 0) {
|
|
reg_to_write |= (1 << i);
|
|
if (--(*cnt) == 0) {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
return reg_to_write;
|
|
}
|
|
|
|
// check range of bits for any coding scheme.
|
|
static bool check_range_of_bits(esp_efuse_block_t blk, int offset_in_bits, int size_bits)
|
|
{
|
|
esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(blk);
|
|
int max_num_bit = offset_in_bits + size_bits;
|
|
if ((scheme == EFUSE_CODING_SCHEME_NONE && max_num_bit > 256) ||
|
|
(scheme == EFUSE_CODING_SCHEME_3_4 && max_num_bit > 192) ||
|
|
(scheme == EFUSE_CODING_SCHEME_REPEAT && max_num_bit > 128)) {
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
static bool read_w_data_and_check_fill(esp_efuse_block_t num_block, uint32_t *buf_w_data)
|
|
{
|
|
bool blk_is_filled = false;
|
|
int i = 0;
|
|
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, ++i) {
|
|
buf_w_data[i] = REG_READ(addr_wr_block);
|
|
if (buf_w_data[i] != 0) {
|
|
REG_WRITE(addr_wr_block, 0);
|
|
blk_is_filled = true;
|
|
}
|
|
}
|
|
return blk_is_filled;
|
|
}
|
|
|
|
static void read_r_data(esp_efuse_block_t num_block, uint32_t* buf_r_data)
|
|
{
|
|
int i = 0;
|
|
for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++i) {
|
|
buf_r_data[i] = REG_READ(addr_rd_block);
|
|
}
|
|
}
|
|
|
|
// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
|
|
// This function reads EFUSE_BLKx_WDATAx_REG registers, applies coding scheme and writes encoded values back to EFUSE_BLKx_WDATAx_REG.
|
|
esp_err_t esp_efuse_utility_apply_new_coding_scheme()
|
|
{
|
|
uint8_t buf_w_data[COUNT_EFUSE_REG_PER_BLOCK * 4];
|
|
uint8_t buf_r_data[COUNT_EFUSE_REG_PER_BLOCK * 4];
|
|
uint32_t reg[COUNT_EFUSE_REG_PER_BLOCK];
|
|
// start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
|
|
for (int num_block = 1; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
|
|
esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(num_block);
|
|
// check and apply a new coding scheme.
|
|
if (scheme != EFUSE_CODING_SCHEME_NONE) {
|
|
memset(buf_w_data, 0, sizeof(buf_w_data));
|
|
memset((uint8_t*)reg, 0, sizeof(reg));
|
|
if (read_w_data_and_check_fill(num_block, (uint32_t*)buf_w_data) == true) {
|
|
read_r_data(num_block, (uint32_t*)buf_r_data);
|
|
if (scheme == EFUSE_CODING_SCHEME_3_4) {
|
|
if (*((uint32_t*)buf_w_data + 6) != 0 || *((uint32_t*)buf_w_data + 7) != 0) {
|
|
return ESP_ERR_CODING;
|
|
}
|
|
for (int i = 0; i < 24; ++i) {
|
|
if (buf_w_data[i] != 0) {
|
|
int st_offset_buf = (i / 6) * 6;
|
|
// check that place is free.
|
|
for (int n = st_offset_buf; n < st_offset_buf + 6; ++n) {
|
|
if (buf_r_data[n] != 0) {
|
|
ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
|
|
return ESP_ERR_CODING;
|
|
}
|
|
}
|
|
|
|
esp_err_t err = esp_efuse_apply_34_encoding(&buf_w_data[st_offset_buf], reg, 6);
|
|
if (err != ESP_OK) {
|
|
return err;
|
|
}
|
|
|
|
int num_reg = (st_offset_buf / 6) * 2;
|
|
for (int r = 0; r < 2; r++) {
|
|
REG_WRITE(range_write_addr_blocks[num_block].start + (num_reg + r) * 4, reg[r]);
|
|
}
|
|
i = st_offset_buf + 5;
|
|
}
|
|
}
|
|
} else if (scheme == EFUSE_CODING_SCHEME_REPEAT) {
|
|
uint32_t* buf_32 = (uint32_t*)buf_w_data;
|
|
for (int i = 4; i < 8; ++i) {
|
|
if (*(buf_32 + i) != 0) {
|
|
return ESP_ERR_CODING;
|
|
}
|
|
}
|
|
for (int i = 0; i < 4; ++i) {
|
|
if (buf_32[i] != 0) {
|
|
REG_WRITE(range_write_addr_blocks[num_block].start + i * 4, buf_32[i]);
|
|
REG_WRITE(range_write_addr_blocks[num_block].start + (i + 4) * 4, buf_32[i]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return ESP_OK;
|
|
}
|