346 lines
13 KiB
C
346 lines
13 KiB
C
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include <stdlib.h>
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#include <sys/cdefs.h>
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#include "esp_log.h"
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#include "esp_eth.h"
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#include "eth_phy_regs_struct.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "driver/gpio.h"
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static const char *TAG = "dm9051";
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#define PHY_CHECK(a, str, goto_tag, ...) \
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do \
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{ \
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if (!(a)) \
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{ \
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ESP_LOGE(TAG, "%s(%d): " str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
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goto goto_tag; \
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} \
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} while (0)
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/***************Vendor Specific Register***************/
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/**
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* @brief DSCR(DAVICOM Specified Configuration Register)
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*
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*/
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typedef union {
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struct {
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uint32_t reserved1 : 1; /* Reserved */
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uint32_t sleep : 1; /* Set 1 to enable PHY into sleep mode */
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uint32_t mfpsc : 1; /* MII frame preamble suppression control bit */
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uint32_t smrst : 1; /* Set 1 to reset all state machines of PHY */
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uint32_t rpdctr_en : 1; /* Set 1 to enable automatic reduced power down */
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uint32_t reserved2 : 2; /* Reserved */
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uint32_t flink100 : 1; /* Force Good Link in 100Mbps */
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uint32_t reserved3 : 2; /* Reserved */
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uint32_t tx_fx : 1; /* 100BASE-TX or FX Mode Control */
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uint32_t reserved4 : 1; /* Reserved */
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uint32_t bp_adpok : 1; /* BYPASS ADPOK */
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uint32_t bp_align : 1; /* Bypass Symbol Alignment Function */
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uint32_t bp_scr : 1; /* Bypass Scrambler/Descrambler Function */
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uint32_t bp_4b5b : 1; /* Bypass 4B5B Encoding and 5B4B Decoding */
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};
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uint32_t val;
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} dscr_reg_t;
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#define ETH_PHY_DSCR_REG_ADDR (0x10)
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/**
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* @brief DSCSR(DAVICOM Specified Configuration and Status Register)
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*
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*/
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typedef union {
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struct {
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uint32_t anmb : 4; /* Auto-Negotiation Monitor Bits */
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uint32_t phy_addr : 5; /* PHY Address */
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uint32_t reserved : 3; /* Reserved */
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uint32_t hdx10 : 1; /* 10M Half-Duplex Operation Mode */
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uint32_t fdx10 : 1; /* 10M Full-Duplex Operation Mode */
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uint32_t hdx100 : 1; /* 100M Half-Duplex Operation Mode */
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uint32_t fdx100 : 1; /* 100M Full-Duplex Operation Mode */
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};
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uint32_t val;
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} dscsr_reg_t;
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#define ETH_PHY_DSCSR_REG_ADDR (0x11)
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typedef struct {
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esp_eth_phy_t parent;
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esp_eth_mediator_t *eth;
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uint32_t addr;
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uint32_t reset_timeout_ms;
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uint32_t autonego_timeout_ms;
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eth_link_t link_status;
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int reset_gpio_num;
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} phy_dm9051_t;
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static esp_err_t dm9051_update_link_duplex_speed(phy_dm9051_t *dm9051)
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{
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esp_eth_mediator_t *eth = dm9051->eth;
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eth_speed_t speed = ETH_SPEED_10M;
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eth_duplex_t duplex = ETH_DUPLEX_HALF;
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bmsr_reg_t bmsr;
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dscsr_reg_t dscsr;
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// BMSR is a latch low register
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// after power up, the first latched value must be 0, which means down
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// to speed up power up link speed, double read this register as a workaround
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PHY_CHECK(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)) == ESP_OK,
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"read BMSR failed", err);
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PHY_CHECK(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)) == ESP_OK,
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"read BMSR failed", err);
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eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
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/* check if link status changed */
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if (dm9051->link_status != link) {
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/* when link up, read negotiation result */
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if (link == ETH_LINK_UP) {
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PHY_CHECK(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_DSCSR_REG_ADDR, &(dscsr.val)) == ESP_OK,
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"read DSCSR failed", err);
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if (dscsr.fdx100 || dscsr.hdx100) {
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speed = ETH_SPEED_100M;
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} else {
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speed = ETH_SPEED_10M;
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}
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if (dscsr.fdx100 || dscsr.fdx10) {
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duplex = ETH_DUPLEX_FULL;
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} else {
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duplex = ETH_DUPLEX_HALF;
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}
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PHY_CHECK(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed) == ESP_OK,
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"change speed failed", err);
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PHY_CHECK(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex) == ESP_OK,
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"change duplex failed", err);
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}
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PHY_CHECK(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link) == ESP_OK,
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"change link failed", err);
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dm9051->link_status = link;
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}
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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static esp_err_t dm9051_set_mediator(esp_eth_phy_t *phy, esp_eth_mediator_t *eth)
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{
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PHY_CHECK(eth, "can't set mediator to null", err);
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phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
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dm9051->eth = eth;
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return ESP_OK;
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err:
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return ESP_ERR_INVALID_ARG;
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}
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static esp_err_t dm9051_get_link(esp_eth_phy_t *phy)
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{
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phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
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/* Updata information about link, speed, duplex */
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PHY_CHECK(dm9051_update_link_duplex_speed(dm9051) == ESP_OK, "update link duplex speed failed", err);
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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static esp_err_t dm9051_reset(esp_eth_phy_t *phy)
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{
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phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
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dm9051->link_status = ETH_LINK_DOWN;
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esp_eth_mediator_t *eth = dm9051->eth;
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dscr_reg_t dscr;
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PHY_CHECK(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_DSCR_REG_ADDR, &(dscr.val)) == ESP_OK,
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"read DSCR failed", err);
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dscr.smrst = 1;
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PHY_CHECK(eth->phy_reg_write(eth, dm9051->addr, ETH_PHY_DSCR_REG_ADDR, dscr.val) == ESP_OK,
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"write DSCR failed", err);
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bmcr_reg_t bmcr = {.reset = 1};
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PHY_CHECK(eth->phy_reg_write(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val) == ESP_OK,
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"write BMCR failed", err);
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/* Wait for reset complete */
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uint32_t to = 0;
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for (to = 0; to < dm9051->reset_timeout_ms / 10; to++) {
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vTaskDelay(pdMS_TO_TICKS(10));
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PHY_CHECK(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)) == ESP_OK,
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"read BMCR failed", err);
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PHY_CHECK(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_DSCR_REG_ADDR, &(dscr.val)) == ESP_OK,
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"read DSCR failed", err);
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if (!bmcr.reset && !dscr.smrst) {
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break;
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}
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}
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PHY_CHECK(to < dm9051->reset_timeout_ms / 10, "PHY reset timeout", err);
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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static esp_err_t dm9051_reset_hw(esp_eth_phy_t *phy)
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{
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phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
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// set reset_gpio_num minus zero can skip hardware reset phy chip
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if (dm9051->reset_gpio_num >= 0) {
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gpio_pad_select_gpio(dm9051->reset_gpio_num);
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gpio_set_direction(dm9051->reset_gpio_num, GPIO_MODE_OUTPUT);
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gpio_set_level(dm9051->reset_gpio_num, 0);
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ets_delay_us(100); // insert min input assert time
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gpio_set_level(dm9051->reset_gpio_num, 1);
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}
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return ESP_OK;
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}
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static esp_err_t dm9051_negotiate(esp_eth_phy_t *phy)
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{
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phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
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esp_eth_mediator_t *eth = dm9051->eth;
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/* Start auto negotiation */
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bmcr_reg_t bmcr = {
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.speed_select = 1, /* 100Mbps */
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.duplex_mode = 1, /* Full Duplex */
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.en_auto_nego = 1, /* Auto Negotiation */
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.restart_auto_nego = 1 /* Restart Auto Negotiation */
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};
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PHY_CHECK(eth->phy_reg_write(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val) == ESP_OK,
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"write BMCR failed", err);
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/* Wait for auto negotiation complete */
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bmsr_reg_t bmsr;
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dscsr_reg_t dscsr;
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uint32_t to = 0;
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for (to = 0; to < dm9051->autonego_timeout_ms / 10; to++) {
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vTaskDelay(pdMS_TO_TICKS(10));
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PHY_CHECK(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)) == ESP_OK,
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"read BMSR failed", err);
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PHY_CHECK(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_DSCSR_REG_ADDR, &(dscsr.val)) == ESP_OK,
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"read DSCSR failed", err);
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if (bmsr.auto_nego_complete && dscsr.anmb & 0x08) {
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break;
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}
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}
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if (to >= dm9051->autonego_timeout_ms / 10) {
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ESP_LOGW(TAG, "Ethernet PHY auto negotiation timeout");
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}
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/* Updata information about link, speed, duplex */
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PHY_CHECK(dm9051_update_link_duplex_speed(dm9051) == ESP_OK, "update link duplex speed failed", err);
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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static esp_err_t dm9051_pwrctl(esp_eth_phy_t *phy, bool enable)
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{
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phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
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esp_eth_mediator_t *eth = dm9051->eth;
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bmcr_reg_t bmcr;
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PHY_CHECK(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)) == ESP_OK,
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"read BMCR failed", err);
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if (!enable) {
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/* Enable IEEE Power Down Mode */
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bmcr.power_down = 1;
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} else {
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/* Disable IEEE Power Down Mode */
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bmcr.power_down = 0;
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}
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PHY_CHECK(eth->phy_reg_write(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val) == ESP_OK,
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"write BMCR failed", err);
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PHY_CHECK(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)) == ESP_OK,
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"read BMCR failed", err);
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if (!enable) {
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PHY_CHECK(bmcr.power_down == 1, "power down failed", err);
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} else {
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PHY_CHECK(bmcr.power_down == 0, "power up failed", err);
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}
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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static esp_err_t dm9051_set_addr(esp_eth_phy_t *phy, uint32_t addr)
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{
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phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
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dm9051->addr = addr;
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return ESP_OK;
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}
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static esp_err_t dm9051_get_addr(esp_eth_phy_t *phy, uint32_t *addr)
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{
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PHY_CHECK(addr, "addr can't be null", err);
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phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
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*addr = dm9051->addr;
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return ESP_OK;
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err:
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return ESP_ERR_INVALID_ARG;
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}
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static esp_err_t dm9051_del(esp_eth_phy_t *phy)
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{
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phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
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free(dm9051);
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return ESP_OK;
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}
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static esp_err_t dm9051_init(esp_eth_phy_t *phy)
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{
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phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
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esp_eth_mediator_t *eth = dm9051->eth;
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/* Power on Ethernet PHY */
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PHY_CHECK(dm9051_pwrctl(phy, true) == ESP_OK, "power control failed", err);
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/* Reset Ethernet PHY */
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PHY_CHECK(dm9051_reset(phy) == ESP_OK, "reset failed", err);
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/* Check PHY ID */
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phyidr1_reg_t id1;
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phyidr2_reg_t id2;
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PHY_CHECK(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_IDR1_REG_ADDR, &(id1.val)) == ESP_OK,
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"read ID1 failed", err);
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PHY_CHECK(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_IDR2_REG_ADDR, &(id2.val)) == ESP_OK,
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"read ID2 failed", err);
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PHY_CHECK(id1.oui_msb == 0x0181 && id2.oui_lsb == 0x2E && id2.vendor_model == 0x0A,
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"wrong chip ID", err);
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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static esp_err_t dm9051_deinit(esp_eth_phy_t *phy)
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{
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/* Power off Ethernet PHY */
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PHY_CHECK(dm9051_pwrctl(phy, false) == ESP_OK, "power control failed", err);
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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esp_eth_phy_t *esp_eth_phy_new_dm9051(const eth_phy_config_t *config)
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{
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PHY_CHECK(config, "can't set phy config to null", err);
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PHY_CHECK(config->phy_addr == 1, "dm9051's phy address can only set to 1", err);
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phy_dm9051_t *dm9051 = calloc(1, sizeof(phy_dm9051_t));
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PHY_CHECK(dm9051, "calloc dm9051 failed", err);
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dm9051->addr = config->phy_addr;
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dm9051->reset_timeout_ms = config->reset_timeout_ms;
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dm9051->reset_gpio_num = config->reset_gpio_num;
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dm9051->link_status = ETH_LINK_DOWN;
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dm9051->autonego_timeout_ms = config->autonego_timeout_ms;
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dm9051->parent.reset = dm9051_reset;
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dm9051->parent.reset_hw = dm9051_reset_hw;
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dm9051->parent.init = dm9051_init;
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dm9051->parent.deinit = dm9051_deinit;
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dm9051->parent.set_mediator = dm9051_set_mediator;
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dm9051->parent.negotiate = dm9051_negotiate;
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dm9051->parent.get_link = dm9051_get_link;
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dm9051->parent.pwrctl = dm9051_pwrctl;
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dm9051->parent.get_addr = dm9051_get_addr;
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dm9051->parent.set_addr = dm9051_set_addr;
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dm9051->parent.del = dm9051_del;
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return &(dm9051->parent);
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err:
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return NULL;
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}
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