Darian Leung 8b1277c55f efuse/add cpu freq rating ... This commit adds support for CPU max freqeuency rating bits in CPU. Bootloader will now print an error if attempting to 160MHz rated ESP32 at 240MHz. EFUSE_CHIP_VER_RESERVE has been replaced by the frequency rating bits. Dependancies on EFUSE_CHIP_VER_RESERVE have been changed to use EFUSE_CHIP_VER_PKG		2018-03-07 12:16:51 +08:00
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include/soc	efuse/add cpu freq rating	2018-03-07 12:16:51 +08:00
test	docs: add information about execution time of ULP instructions	2017-12-11 14:05:41 +08:00
cpu_util.c	esp_restart: fix possible race while stalling other CPU, enable WDT early	2017-10-26 19:53:53 +08:00
i2c_apll.h	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
i2c_bbpll.h	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
i2c_rtc_clk.h	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
rtc_clk.c	soc/rtc_clk: fix loss of precision in estimation of XTAL frequency	2018-01-08 23:31:21 +08:00
rtc_init.c	esp_adc_cal/Add eFuse functionality	2018-02-13 21:22:48 +08:00
rtc_pm.c	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
rtc_sleep.c	soc/rtc: add function to get/set VDDSDIO configuration	2017-11-03 15:49:09 +08:00
rtc_time.c	soc/rtc: add a function to wait for slow clock cycle	2017-10-26 19:53:53 +08:00
soc_log.h	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
soc_memory_layout.c	Add logic to make external RAM usable with malloc()	2017-09-28 17:17:50 +08:00