a049e02d96
The following commit refactors the CAN driver such that it is split into HAL and Lowlevel layers. The following changes have also been made: - Added bit field members to can_message_t as alternative to message flags. Updated examples and docs accordingly - Register field names and fields of can_dev_t updated
704 lines
22 KiB
C
704 lines
22 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*******************************************************************************
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* NOTICE
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* The ll is not public api, don't use in application code.
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* See readme.md in soc/include/hal/readme.md
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******************************************************************************/
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// The Lowlevel layer for CAN
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/can_types.h"
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#include "soc/can_periph.h"
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/* ------------------------- Defines and Typedefs --------------------------- */
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#define CAN_LL_STATUS_RBS (0x1 << 0)
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#define CAN_LL_STATUS_DOS (0x1 << 1)
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#define CAN_LL_STATUS_TBS (0x1 << 2)
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#define CAN_LL_STATUS_TCS (0x1 << 3)
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#define CAN_LL_STATUS_RS (0x1 << 4)
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#define CAN_LL_STATUS_TS (0x1 << 5)
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#define CAN_LL_STATUS_ES (0x1 << 6)
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#define CAN_LL_STATUS_BS (0x1 << 7)
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#define CAN_LL_INTR_RI (0x1 << 0)
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#define CAN_LL_INTR_TI (0x1 << 1)
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#define CAN_LL_INTR_EI (0x1 << 2)
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//Data overrun interrupt not supported in SW due to HW peculiarities
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#define CAN_LL_INTR_EPI (0x1 << 5)
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#define CAN_LL_INTR_ALI (0x1 << 6)
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#define CAN_LL_INTR_BEI (0x1 << 7)
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/*
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* The following frame structure has an NEARLY identical bit field layout to
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* each byte of the TX buffer. This allows for formatting and parsing frames to
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* be done outside of time critical regions (i.e., ISRs). All the ISR needs to
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* do is to copy byte by byte to/from the TX/RX buffer. The two reserved bits in
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* TX buffer are used in the frame structure to store the self_reception and
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* single_shot flags which in turn indicate the type of transmission to execute.
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*/
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typedef union {
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struct {
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struct {
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uint8_t dlc: 4; //Data length code (0 to 8) of the frame
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uint8_t self_reception: 1; //This frame should be transmitted using self reception command
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uint8_t single_shot: 1; //This frame should be transmitted using single shot command
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uint8_t rtr: 1; //This frame is a remote transmission request
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uint8_t frame_format: 1; //Format of the frame (1 = extended, 0 = standard)
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};
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union {
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struct {
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uint8_t id[2]; //11 bit standard frame identifier
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uint8_t data[8]; //Data bytes (0 to 8)
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uint8_t reserved8[2];
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} standard;
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struct {
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uint8_t id[4]; //29 bit extended frame identifier
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uint8_t data[8]; //Data bytes (0 to 8)
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} extended;
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};
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};
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uint8_t bytes[13];
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} __attribute__((packed)) can_ll_frame_buffer_t;
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/* ---------------------------- Mode Register ------------------------------- */
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/**
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* @brief Enter reset mode
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*
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* When in reset mode, the CAN controller is effectively disconnected from the
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* CAN bus and will not participate in any bus activates. Reset mode is required
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* in order to write the majority of configuration registers.
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*
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* @param hw Start address of the CAN registers
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* @return true if reset mode was entered successfully
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*
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* @note Reset mode is automatically entered on BUS OFF condition
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*/
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static inline bool can_ll_enter_reset_mode(can_dev_t *hw)
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{
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hw->mode_reg.rm = 1;
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return hw->mode_reg.rm;
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}
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/**
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* @brief Exit reset mode
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*
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* When not in reset mode, the CAN controller will take part in bus activities
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* (e.g., send/receive/acknowledge messages and error frames) depending on the
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* operating mode.
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*
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* @param hw Start address of the CAN registers
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* @return true if reset mode was exit successfully
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*
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* @note Reset mode must be exit to initiate BUS OFF recovery
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*/
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static inline bool can_ll_exit_reset_mode(can_dev_t *hw)
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{
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hw->mode_reg.rm = 0;
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return !(hw->mode_reg.rm);
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}
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/**
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* @brief Check if in reset mode
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* @param hw Start address of the CAN registers
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* @return true if in reset mode
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*/
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static inline bool can_ll_is_in_reset_mode(can_dev_t *hw)
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{
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return hw->mode_reg.rm;
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}
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/**
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* @brief Set operating mode of CAN controller
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*
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* @param hw Start address of the CAN registers
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* @param mode Operating mode
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*
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* @note Must be called in reset mode
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*/
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static inline void can_ll_set_mode(can_dev_t *hw, can_mode_t mode)
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{
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if (mode == CAN_MODE_NORMAL) { //Normal Operating mode
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hw->mode_reg.lom = 0;
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hw->mode_reg.stm = 0;
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} else if (mode == CAN_MODE_NO_ACK) { //Self Test Mode (No Ack)
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hw->mode_reg.lom = 0;
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hw->mode_reg.stm = 1;
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} else if (mode == CAN_MODE_LISTEN_ONLY) { //Listen Only Mode
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hw->mode_reg.lom = 1;
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hw->mode_reg.stm = 0;
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}
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}
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/* --------------------------- Command Register ----------------------------- */
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/**
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* @brief Set TX command
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*
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* Setting the TX command will cause the CAN controller to attempt to transmit
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* the frame stored in the TX buffer. The TX buffer will be occupied (i.e.,
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* locked) until TX completes.
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*
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* @param hw Start address of the CAN registers
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*
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* @note Transmit commands should be called last (i.e., after handling buffer
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* release and clear data overrun) in order to prevent the other commands
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* overwriting this latched TX bit with 0.
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*/
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static inline void can_ll_set_cmd_tx(can_dev_t *hw)
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{
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hw->command_reg.tr = 1;
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}
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/**
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* @brief Set single shot TX command
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*
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* Similar to setting TX command, but the CAN controller will not automatically
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* retry transmission upon an error (e.g., due to an acknowledgement error).
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*
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* @param hw Start address of the CAN registers
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*
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* @note Transmit commands should be called last (i.e., after handling buffer
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* release and clear data overrun) in order to prevent the other commands
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* overwriting this latched TX bit with 0.
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*/
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static inline void can_ll_set_cmd_tx_single_shot(can_dev_t *hw)
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{
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hw->command_reg.val = 0x03; //Writing to TR and AT simultaneously
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}
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/**
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* @brief Aborts TX
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*
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* Frames awaiting TX will be aborted. Frames already being TX are not aborted.
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* Transmission Complete Status bit is automatically set to 1.
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* Similar to setting TX command, but the CAN controller will not automatically
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* retry transmission upon an error (e.g., due to acknowledge error).
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*
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* @param hw Start address of the CAN registers
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*
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* @note Transmit commands should be called last (i.e., after handling buffer
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* release and clear data overrun) in order to prevent the other commands
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* overwriting this latched TX bit with 0.
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*/
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static inline void can_ll_set_cmd_abort_tx(can_dev_t *hw)
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{
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hw->command_reg.at = 1;
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}
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/**
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* @brief Release RX buffer
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*
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* Rotates RX buffer to the next frame in the RX FIFO.
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*
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* @param hw Start address of the CAN registers
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*/
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static inline void can_ll_set_cmd_release_rx_buffer(can_dev_t *hw)
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{
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hw->command_reg.rrb = 1;
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}
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/**
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* @brief Clear data overrun
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*
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* Clears the data overrun status bit
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*
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* @param hw Start address of the CAN registers
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*/
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static inline void can_ll_set_cmd_clear_data_overrun(can_dev_t *hw)
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{
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hw->command_reg.cdo = 1;
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}
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/**
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* @brief Set self reception single shot command
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*
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* Similar to setting TX command, but the CAN controller also simultaneously
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* receive the transmitted frame and is generally used for self testing
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* purposes. The CAN controller will not ACK the received message, so consider
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* using the NO_ACK operating mode.
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*
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* @param hw Start address of the CAN registers
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*
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* @note Transmit commands should be called last (i.e., after handling buffer
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* release and clear data overrun) in order to prevent the other commands
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* overwriting this latched TX bit with 0.
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*/
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static inline void can_ll_set_cmd_self_rx_request(can_dev_t *hw)
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{
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hw->command_reg.srr = 1;
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}
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/**
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* @brief Set self reception request command
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*
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* Similar to setting the self reception request, but the CAN controller will
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* not automatically retry transmission upon an error (e.g., due to and
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* acknowledgement error).
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*
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* @param hw Start address of the CAN registers
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*
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* @note Transmit commands should be called last (i.e., after handling buffer
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* release and clear data overrun) in order to prevent the other commands
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* overwriting this latched TX bit with 0.
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*/
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static inline void can_ll_set_cmd_self_rx_single_shot(can_dev_t *hw)
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{
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hw->command_reg.val = 0x12;
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}
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/* --------------------------- Status Register ------------------------------ */
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/**
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* @brief Get all status bits
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*
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* @param hw Start address of the CAN registers
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* @return Status bits
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*/
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static inline uint32_t can_ll_get_status(can_dev_t *hw)
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{
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return hw->status_reg.val;
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}
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/**
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* @brief Check if RX FIFO overrun status bit is set
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*
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* @param hw Start address of the CAN registers
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* @return Overrun status bit
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*/
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static inline bool can_ll_is_fifo_overrun(can_dev_t *hw)
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{
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return hw->status_reg.dos;
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}
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/**
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* @brief Check if previously TX was successful
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*
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* @param hw Start address of the CAN registers
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* @return Whether previous TX was successful
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*/
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static inline bool can_ll_is_last_tx_successful(can_dev_t *hw)
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{
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return hw->status_reg.tcs;
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}
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//Todo: Add stand alone status bit check functions when necessary
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/* -------------------------- Interrupt Register ---------------------------- */
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/**
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* @brief Get currently set interrupts
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*
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* Reading the interrupt registers will automatically clear all interrupts
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* except for the Receive Interrupt.
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*
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* @param hw Start address of the CAN registers
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* @return Bit mask of set interrupts
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*/
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static inline uint32_t can_ll_get_and_clear_intrs(can_dev_t *hw)
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{
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return hw->interrupt_reg.val;
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}
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/* ----------------------- Interrupt Enable Register ------------------------ */
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/**
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* @brief Set which interrupts are enabled
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*
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* @param hw Start address of the CAN registers
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* @param Bit mask of interrupts to enable
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*
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* @note Must be called in reset mode
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*/
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static inline void can_ll_set_enabled_intrs(can_dev_t *hw, uint32_t intr_mask)
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{
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#ifdef CAN_BRP_DIV_SUPPORTED
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//ESP32 Rev 2 has brp div. Need to mask when setting
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hw->interrupt_enable_reg.val = (hw->interrupt_enable_reg.val & 0x10) | intr_mask;
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#else
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hw->interrupt_enable_reg.val = intr_mask;
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#endif
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}
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/* ------------------------ Bus Timing Registers --------------------------- */
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/**
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* @brief Set bus timing
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*
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* @param hw Start address of the CAN registers
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* @param brp Baud Rate Prescaler
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* @param sjw Synchronization Jump Width
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* @param tseg1 Timing Segment 1
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* @param tseg2 Timing Segment 2
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* @param triple_sampling Triple Sampling enable/disable
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*
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* @note Must be called in reset mode
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* @note ESP32 rev 2 or later can support a x2 brp by setting a brp_div bit,
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* allowing the brp to go from a maximum of 128 to 256.
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*/
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static inline void can_ll_set_bus_timing(can_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling)
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{
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#ifdef CAN_BRP_DIV_SUPPORTED
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if (brp > CAN_BRP_DIV_THRESH) {
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//Need to set brp_div bit
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hw->interrupt_enable_reg.brp_div = 1;
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brp /= 2;
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}
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#endif
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hw->bus_timing_0_reg.brp = (brp / 2) - 1;
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hw->bus_timing_0_reg.sjw = sjw - 1;
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hw->bus_timing_1_reg.tseg1 = tseg1 - 1;
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hw->bus_timing_1_reg.tseg2 = tseg2 - 1;
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hw->bus_timing_1_reg.sam = triple_sampling;
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}
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/* ----------------------------- ALC Register ------------------------------- */
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/**
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* @brief Clear Arbitration Lost Capture Register
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*
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* Reading the ALC register rearms the Arbitration Lost Interrupt
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*
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* @param hw Start address of the CAN registers
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*/
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static inline void can_ll_clear_arb_lost_cap(can_dev_t *hw)
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{
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(void)hw->arbitration_lost_captue_reg.val;
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//Todo: Decode ALC register
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}
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/* ----------------------------- ECC Register ------------------------------- */
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/**
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* @brief Clear Error Code Capture register
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*
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* Reading the ECC register rearms the Bus Error Interrupt
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*
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* @param hw Start address of the CAN registers
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*/
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static inline void can_ll_clear_err_code_cap(can_dev_t *hw)
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{
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(void)hw->error_code_capture_reg.val;
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//Todo: Decode error code capture
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}
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/* ----------------------------- EWL Register ------------------------------- */
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/**
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* @brief Set Error Warning Limit
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*
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* @param hw Start address of the CAN registers
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* @param ewl Error Warning Limit
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*
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* @note Must be called in reset mode
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*/
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static inline void can_ll_set_err_warn_lim(can_dev_t *hw, uint32_t ewl)
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{
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hw->error_warning_limit_reg.ewl = ewl;
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}
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/**
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* @brief Get Error Warning Limit
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*
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* @param hw Start address of the CAN registers
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* @return Error Warning Limit
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*/
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static inline uint32_t can_ll_get_err_warn_lim(can_dev_t *hw)
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{
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return hw->error_warning_limit_reg.val;
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}
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/* ------------------------ RX Error Count Register ------------------------- */
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/**
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* @brief Get RX Error Counter
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*
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* @param hw Start address of the CAN registers
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* @return REC value
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*
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* @note REC is not frozen in reset mode. Listen only mode will freeze it. A BUS
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* OFF condition automatically sets the REC to 0.
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*/
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static inline uint32_t can_ll_get_rec(can_dev_t *hw)
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{
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return hw->rx_error_counter_reg.val;
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}
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/**
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* @brief Set RX Error Counter
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*
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* @param hw Start address of the CAN registers
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* @param rec REC value
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*
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* @note Must be called in reset mode
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*/
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static inline void can_ll_set_rec(can_dev_t *hw, uint32_t rec)
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{
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hw->rx_error_counter_reg.rxerr = rec;
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}
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/* ------------------------ TX Error Count Register ------------------------- */
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/**
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* @brief Get TX Error Counter
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*
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* @param hw Start address of the CAN registers
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* @return TEC value
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*
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* @note A BUS OFF condition will automatically set this to 128
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*/
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static inline uint32_t can_ll_get_tec(can_dev_t *hw)
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{
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return hw->tx_error_counter_reg.val;
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}
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/**
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* @brief Set TX Error Counter
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*
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* @param hw Start address of the CAN registers
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* @param tec TEC value
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*
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* @note Must be called in reset mode
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*/
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static inline void can_ll_set_tec(can_dev_t *hw, uint32_t tec)
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{
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hw->tx_error_counter_reg.txerr = tec;
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}
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/* ---------------------- Acceptance Filter Registers ----------------------- */
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/**
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* @brief Set Acceptance Filter
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* @param hw Start address of the CAN registers
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* @param code Acceptance Code
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* @param mask Acceptance Mask
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* @param single_filter Whether to enable single filter mode
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*
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* @note Must be called in reset mode
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*/
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static inline void can_ll_set_acc_filter(can_dev_t* hw, uint32_t code, uint32_t mask, bool single_filter)
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{
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uint32_t code_swapped = __builtin_bswap32(code);
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uint32_t mask_swapped = __builtin_bswap32(mask);
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for (int i = 0; i < 4; i++) {
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hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
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hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
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}
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hw->mode_reg.afm = single_filter;
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}
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/* ------------------------- TX/RX Buffer Registers ------------------------- */
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/**
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* @brief Copy a formatted CAN frame into TX buffer for transmission
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*
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* @param hw Start address of the CAN registers
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* @param tx_frame Pointer to formatted frame
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*
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* @note Call can_ll_format_frame_buffer() to format a frame
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*/
|
|
static inline void can_ll_set_tx_buffer(can_dev_t *hw, can_ll_frame_buffer_t *tx_frame)
|
|
{
|
|
//Copy formatted frame into TX buffer
|
|
for (int i = 0; i < 13; i++) {
|
|
hw->tx_rx_buffer[i].val = tx_frame->bytes[i];
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Copy a received frame from the RX buffer for parsing
|
|
*
|
|
* @param hw Start address of the CAN registers
|
|
* @param rx_frame Pointer to store formatted frame
|
|
*
|
|
* @note Call can_ll_prase_frame_buffer() to parse the formatted frame
|
|
*/
|
|
static inline void can_ll_get_rx_buffer(can_dev_t *hw, can_ll_frame_buffer_t *rx_frame)
|
|
{
|
|
//Copy RX buffer registers into frame
|
|
for (int i = 0; i < 13; i++) {
|
|
rx_frame->bytes[i] = hw->tx_rx_buffer[i].byte;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Format contents of a CAN frame into layout of TX Buffer
|
|
*
|
|
* @param[in] id 11 or 29bit ID
|
|
* @param[in] dlc Data length code
|
|
* @param[in] data Pointer to an 8 byte array containing data. NULL if no data
|
|
* @param[in] format Type of CAN frame
|
|
* @param[in] single_shot Frame will not be retransmitted on failure
|
|
* @param[in] self_rx Frame will also be simultaneously received
|
|
* @param[out] tx_frame Pointer to store formatted frame
|
|
*/
|
|
static inline void can_ll_format_frame_buffer(uint32_t id, uint8_t dlc, const uint8_t *data,
|
|
uint32_t flags, can_ll_frame_buffer_t *tx_frame)
|
|
{
|
|
/* This function encodes a message into a frame structure. The frame structure has
|
|
an identical layout to the TX buffer, allowing the frame structure to be directly
|
|
copied into TX buffer. */
|
|
bool is_extd = flags & CAN_MSG_FLAG_EXTD;
|
|
bool is_rtr = flags & CAN_MSG_FLAG_RTR;
|
|
|
|
//Set frame information
|
|
tx_frame->dlc = dlc;
|
|
tx_frame->frame_format = is_extd;
|
|
tx_frame->rtr = is_rtr;
|
|
tx_frame->self_reception = (flags & CAN_MSG_FLAG_SELF) ? 1 : 0;
|
|
tx_frame->single_shot = (flags & CAN_MSG_FLAG_SS) ? 1 : 0;
|
|
|
|
//Set ID
|
|
if (is_extd) {
|
|
uint32_t id_temp = __builtin_bswap32((id & CAN_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i))
|
|
for (int i = 0; i < 4; i++) {
|
|
tx_frame->extended.id[i] = (id_temp >> (8 * i)) & 0xFF;
|
|
}
|
|
} else {
|
|
uint32_t id_temp = __builtin_bswap16((id & CAN_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i))
|
|
for (int i = 0; i < 2; i++) {
|
|
tx_frame->standard.id[i] = (id_temp >> (8 * i)) & 0xFF;
|
|
}
|
|
}
|
|
|
|
//Set Data
|
|
uint8_t *data_buffer = (is_extd) ? tx_frame->extended.data : tx_frame->standard.data;
|
|
if (!is_rtr) {
|
|
for (int i = 0; (i < dlc) && (i < CAN_FRAME_MAX_DLC); i++) {
|
|
data_buffer[i] = data[i];
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Parse formatted CAN frame (RX Buffer Layout) into its contents
|
|
*
|
|
* @param[in] rx_frame Pointer to formatted frame
|
|
* @param[out] id 11 or 29bit ID
|
|
* @param[out] dlc Data length code
|
|
* @param[out] data Data. Left over bytes set to 0.
|
|
* @param[out] format Type of CAN frame
|
|
*/
|
|
static inline void can_ll_prase_frame_buffer(can_ll_frame_buffer_t *rx_frame, uint32_t *id, uint8_t *dlc,
|
|
uint8_t *data, uint32_t *flags)
|
|
{
|
|
//This function decodes a frame structure into it's constituent components.
|
|
|
|
//Copy frame information
|
|
*dlc = rx_frame->dlc;
|
|
uint32_t flags_temp = 0;
|
|
flags_temp |= (rx_frame->frame_format) ? CAN_MSG_FLAG_EXTD : 0;
|
|
flags_temp |= (rx_frame->rtr) ? CAN_MSG_FLAG_RTR : 0;
|
|
flags_temp |= (rx_frame->dlc > CAN_FRAME_MAX_DLC) ? CAN_MSG_FLAG_DLC_NON_COMP : 0;
|
|
*flags = flags_temp;
|
|
|
|
//Copy ID
|
|
if (rx_frame->frame_format) {
|
|
uint32_t id_temp = 0;
|
|
for (int i = 0; i < 4; i++) {
|
|
id_temp |= rx_frame->extended.id[i] << (8 * i);
|
|
}
|
|
id_temp = __builtin_bswap32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3)
|
|
*id = id_temp & CAN_EXTD_ID_MASK;
|
|
} else {
|
|
uint32_t id_temp = 0;
|
|
for (int i = 0; i < 2; i++) {
|
|
id_temp |= rx_frame->standard.id[i] << (8 * i);
|
|
}
|
|
id_temp = __builtin_bswap16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5)
|
|
*id = id_temp & CAN_STD_ID_MASK;
|
|
}
|
|
|
|
//Copy data
|
|
uint8_t *data_buffer = (rx_frame->frame_format) ? rx_frame->extended.data : rx_frame->standard.data;
|
|
int data_length = (rx_frame->rtr) ? 0 : ((rx_frame->dlc > CAN_FRAME_MAX_DLC) ? CAN_FRAME_MAX_DLC : rx_frame->dlc);
|
|
for (int i = 0; i < data_length; i++) {
|
|
data[i] = data_buffer[i];
|
|
}
|
|
//Set remaining bytes of data to 0
|
|
for (int i = data_length; i < CAN_FRAME_MAX_DLC; i++) {
|
|
data[i] = 0;
|
|
}
|
|
}
|
|
|
|
/* ----------------------- RX Message Count Register ------------------------ */
|
|
|
|
/**
|
|
* @brief Get RX Message Counter
|
|
*
|
|
* @param hw Start address of the CAN registers
|
|
* @return RX Message Counter
|
|
*/
|
|
static inline uint32_t can_ll_get_rx_msg_count(can_dev_t *hw)
|
|
{
|
|
return hw->rx_message_counter_reg.val;
|
|
}
|
|
|
|
/* ------------------------- Clock Divider Register ------------------------- */
|
|
|
|
/**
|
|
* @brief Set CLKOUT Divider and enable/disable
|
|
*
|
|
* @param hw Start address of the CAN registers
|
|
* @param divider Divider for CLKOUT. Set to 0 to disable CLKOUT
|
|
*/
|
|
static inline void can_ll_set_clkout(can_dev_t *hw, uint32_t divider)
|
|
{
|
|
/* Configure CLKOUT. CLKOUT is a pre-scaled version of APB CLK. Divider can be
|
|
1, or any even number from 2 to 14. Set to out of range value (0) to disable
|
|
CLKOUT. */
|
|
|
|
if (divider >= 2 && divider <= 14) {
|
|
CAN.clock_divider_reg.co = 0;
|
|
CAN.clock_divider_reg.cd = (divider / 2) - 1;
|
|
} else if (divider == 1) {
|
|
CAN.clock_divider_reg.co = 0;
|
|
CAN.clock_divider_reg.cd = 7;
|
|
} else {
|
|
CAN.clock_divider_reg.co = 1;
|
|
CAN.clock_divider_reg.cd = 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Set register address mapping to extended mode
|
|
*
|
|
* Extended mode register address mapping consists of more registers and extra
|
|
* features.
|
|
*
|
|
* @param hw Start address of the CAN registers
|
|
*
|
|
* @note Must be called before setting any configuration
|
|
* @note Must be called in reset mode
|
|
*/
|
|
static inline void can_ll_enable_extended_reg_layout(can_dev_t *hw)
|
|
{
|
|
hw->clock_divider_reg.cm = 1;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|