288 lines
8.8 KiB
C
288 lines
8.8 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include <assert.h>
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#include <string.h>
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#include <stdio.h>
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#include <freertos/FreeRTOS.h>
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#include <freertos/task.h>
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#include <freertos/semphr.h>
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#include <rom/spi_flash.h>
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#include <rom/cache.h>
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#include <soc/soc.h>
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#include <soc/dport_reg.h>
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#include "sdkconfig.h"
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#include "esp_ipc.h"
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#include "esp_attr.h"
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#include "esp_spi_flash.h"
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#include "esp_log.h"
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#include "cache_utils.h"
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/* bytes erased by SPIEraseBlock() ROM function */
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#define BLOCK_ERASE_SIZE 65536
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#if CONFIG_SPI_FLASH_ENABLE_COUNTERS
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static const char* TAG = "spi_flash";
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static spi_flash_counters_t s_flash_stats;
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#define COUNTER_START() uint32_t ts_begin = xthal_get_ccount()
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#define COUNTER_STOP(counter) \
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do{ \
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s_flash_stats.counter.count++; \
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s_flash_stats.counter.time += (xthal_get_ccount() - ts_begin) / (XT_CLOCK_FREQ / 1000000); \
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} while(0)
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#define COUNTER_ADD_BYTES(counter, size) \
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do { \
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s_flash_stats.counter.bytes += size; \
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} while (0)
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#else
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#define COUNTER_START()
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#define COUNTER_STOP(counter)
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#define COUNTER_ADD_BYTES(counter, size)
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#endif //CONFIG_SPI_FLASH_ENABLE_COUNTERS
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static esp_err_t spi_flash_translate_rc(SpiFlashOpResult rc);
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void spi_flash_init()
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{
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spi_flash_init_lock();
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#if CONFIG_SPI_FLASH_ENABLE_COUNTERS
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spi_flash_reset_counters();
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#endif
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}
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size_t spi_flash_get_chip_size()
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{
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return g_rom_flashchip.chip_size;
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}
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SpiFlashOpResult IRAM_ATTR spi_flash_unlock()
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{
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static bool unlocked = false;
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if (!unlocked) {
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SpiFlashOpResult rc = SPIUnlock();
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if (rc != SPI_FLASH_RESULT_OK) {
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return rc;
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}
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unlocked = true;
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}
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return SPI_FLASH_RESULT_OK;
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}
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esp_err_t IRAM_ATTR spi_flash_erase_sector(size_t sec)
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{
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return spi_flash_erase_range(sec * SPI_FLASH_SEC_SIZE, SPI_FLASH_SEC_SIZE);
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}
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esp_err_t IRAM_ATTR spi_flash_erase_range(uint32_t start_addr, uint32_t size)
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{
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if (start_addr % SPI_FLASH_SEC_SIZE != 0) {
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return ESP_ERR_INVALID_ARG;
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}
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if (size % SPI_FLASH_SEC_SIZE != 0) {
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return ESP_ERR_INVALID_SIZE;
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}
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if (size + start_addr > spi_flash_get_chip_size()) {
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return ESP_ERR_INVALID_SIZE;
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}
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size_t start = start_addr / SPI_FLASH_SEC_SIZE;
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size_t end = start + size / SPI_FLASH_SEC_SIZE;
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const size_t sectors_per_block = BLOCK_ERASE_SIZE / SPI_FLASH_SEC_SIZE;
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COUNTER_START();
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spi_flash_disable_interrupts_caches_and_other_cpu();
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SpiFlashOpResult rc;
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rc = spi_flash_unlock();
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if (rc == SPI_FLASH_RESULT_OK) {
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for (size_t sector = start; sector != end && rc == SPI_FLASH_RESULT_OK; ) {
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if (sector % sectors_per_block == 0 && end - sector > sectors_per_block) {
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rc = SPIEraseBlock(sector / sectors_per_block);
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sector += sectors_per_block;
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COUNTER_ADD_BYTES(erase, sectors_per_block * SPI_FLASH_SEC_SIZE);
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}
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else {
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rc = SPIEraseSector(sector);
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++sector;
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COUNTER_ADD_BYTES(erase, SPI_FLASH_SEC_SIZE);
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}
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}
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}
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spi_flash_enable_interrupts_caches_and_other_cpu();
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COUNTER_STOP(erase);
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return spi_flash_translate_rc(rc);
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}
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esp_err_t IRAM_ATTR spi_flash_write(size_t dest_addr, const void *src, size_t size)
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{
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// Destination alignment is also checked in ROM code, but we can give
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// better error code here
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// TODO: add handling of unaligned destinations
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uint8_t *temp_write_buf = NULL;
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uint8_t pad_head = 0;
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uint8_t pad_end = 0;
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SpiFlashOpResult rc;
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// Out of bound writes are checked in ROM code, but we can give better
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// error code here
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if (dest_addr + size > g_rom_flashchip.chip_size) {
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return ESP_ERR_INVALID_SIZE;
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}
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while(size >= 1024) {
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// max need pad byte num for 1024 is 4
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temp_write_buf = (uint8_t*)malloc(1024 + 4);
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if(temp_write_buf == NULL) {
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return ESP_ERR_NO_MEM;
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}
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if(dest_addr%4 != 0) {
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pad_head = dest_addr%4;
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pad_end = 4 - pad_head;
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}
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memset(temp_write_buf,0xFF,pad_head);
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memcpy(temp_write_buf + pad_head ,src,1024);
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memset(temp_write_buf + pad_head + 1024, 0xFF,pad_end);
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COUNTER_START();
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spi_flash_disable_interrupts_caches_and_other_cpu();
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rc = spi_flash_unlock();
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if (rc == SPI_FLASH_RESULT_OK) {
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rc = SPIWrite((uint32_t) (dest_addr - pad_head), (const uint32_t*) temp_write_buf, (int32_t) (1024 + pad_head + pad_end));
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COUNTER_ADD_BYTES(write, 1024 + pad_head + pad_end);
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}
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COUNTER_STOP(write);
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spi_flash_enable_interrupts_caches_and_other_cpu();
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if(rc != ESP_OK) {
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free(temp_write_buf);
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temp_write_buf = NULL;
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return spi_flash_translate_rc(rc);
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}
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free(temp_write_buf);
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temp_write_buf = NULL;
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size -= 1024;
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dest_addr += 1024;
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src = (uint8_t*)src + 1024;
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}
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if(size > 0) {
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// max need pad byte num for rand size is 6
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temp_write_buf = (uint8_t*)malloc(size + 6);
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if(temp_write_buf == NULL) {
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return ESP_ERR_NO_MEM;
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}
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if(dest_addr%4 != 0) {
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pad_head = dest_addr%4;
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}
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if ((pad_head + size)%4 != 0){
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pad_end = 4 - (pad_head + size) % 4;
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}
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memset(temp_write_buf,0xFF,pad_head);
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memcpy(temp_write_buf + pad_head, src, size);
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memset(temp_write_buf + pad_head + size, 0xFF,pad_end);
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COUNTER_START();
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spi_flash_disable_interrupts_caches_and_other_cpu();
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rc = spi_flash_unlock();
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if (rc == SPI_FLASH_RESULT_OK) {
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rc = SPIWrite((uint32_t) (dest_addr - pad_head), (const uint32_t*) temp_write_buf, (int32_t) (size + pad_head + pad_end));
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COUNTER_ADD_BYTES(write, size + pad_head + pad_end);
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}
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COUNTER_STOP(write);
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spi_flash_enable_interrupts_caches_and_other_cpu();
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if(rc != ESP_OK) {
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free(temp_write_buf);
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temp_write_buf = NULL;
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return spi_flash_translate_rc(rc);
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}
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free(temp_write_buf);
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temp_write_buf = NULL;
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size = 0;
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dest_addr += size;
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src = (uint8_t*)src + size;
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return spi_flash_translate_rc(rc);
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}
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return spi_flash_translate_rc(SPI_FLASH_RESULT_OK);
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}
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esp_err_t IRAM_ATTR spi_flash_read(size_t src_addr, void *dest, size_t size)
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{
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// TODO: replace this check with code which deals with unaligned destinations
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if (((ptrdiff_t) dest) % 4 != 0) {
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return ESP_ERR_INVALID_ARG;
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}
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// Source alignment is also checked in ROM code, but we can give
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// better error code here
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// TODO: add handling of unaligned destinations
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if (src_addr % 4 != 0) {
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return ESP_ERR_INVALID_ARG;
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}
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if (size % 4 != 0) {
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return ESP_ERR_INVALID_SIZE;
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}
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// Out of bound reads are checked in ROM code, but we can give better
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// error code here
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if (src_addr + size > g_rom_flashchip.chip_size) {
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return ESP_ERR_INVALID_SIZE;
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}
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COUNTER_START();
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spi_flash_disable_interrupts_caches_and_other_cpu();
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SpiFlashOpResult rc = SPIRead((uint32_t) src_addr, (uint32_t*) dest, (int32_t) size);
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COUNTER_ADD_BYTES(read, size);
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spi_flash_enable_interrupts_caches_and_other_cpu();
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COUNTER_STOP(read);
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return spi_flash_translate_rc(rc);
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}
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static esp_err_t spi_flash_translate_rc(SpiFlashOpResult rc)
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{
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switch (rc) {
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case SPI_FLASH_RESULT_OK:
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return ESP_OK;
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case SPI_FLASH_RESULT_TIMEOUT:
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return ESP_ERR_FLASH_OP_TIMEOUT;
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case SPI_FLASH_RESULT_ERR:
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default:
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return ESP_ERR_FLASH_OP_FAIL;
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}
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}
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#if CONFIG_SPI_FLASH_ENABLE_COUNTERS
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static inline void dump_counter(spi_flash_counter_t* counter, const char* name)
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{
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ESP_LOGI(TAG, "%s count=%8d time=%8dms bytes=%8d\n", name,
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counter->count, counter->time, counter->bytes);
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}
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const spi_flash_counters_t* spi_flash_get_counters()
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{
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return &s_flash_stats;
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}
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void spi_flash_reset_counters()
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{
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memset(&s_flash_stats, 0, sizeof(s_flash_stats));
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}
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void spi_flash_dump_counters()
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{
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dump_counter(&s_flash_stats.read, "read ");
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dump_counter(&s_flash_stats.write, "write");
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dump_counter(&s_flash_stats.erase, "erase");
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}
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#endif //CONFIG_SPI_FLASH_ENABLE_COUNTERS
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