OVMS3-idf/components/soc
Taavi Hein 8b6060e24e gpio: Bitmask overflow fix in gpio_reset_pin
For pins 32 and up the BIT(nr) macro used here overflowed,
causing undetermined GPIO pins to be reset.
Example: freeing SPI device/bus where CS is on pin 33
caused debug UART to cease communication, TXD0 was
disabled.

Fixed as BIT64(nr) macro, to be used elsewhere as needed.
For example in definitions like GPIO_SEL_32..GPIO_SEL_39.
2018-08-14 04:23:56 +03:00
..
esp32 gpio: Bitmask overflow fix in gpio_reset_pin 2018-08-14 04:23:56 +03:00
include/soc soc: Fix check_long_hold_gpio and move def to soc 2018-06-26 12:47:55 +05:00
test soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
component.mk Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet. 2017-09-04 12:05:49 +08:00