304 lines
11 KiB
C
304 lines
11 KiB
C
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include <stdlib.h>
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#include <sys/cdefs.h>
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#include "esp_log.h"
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#include "esp_eth.h"
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#include "eth_phy_regs_struct.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "driver/gpio.h"
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static const char *TAG = "enc28j60";
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#define PHY_CHECK(a, str, goto_tag, ...) \
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do \
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{ \
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if (!(a)) \
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{ \
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ESP_LOGE(TAG, "%s(%d): " str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
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goto goto_tag; \
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} \
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} while (0)
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/***************Vendor Specific Register***************/
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/**
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* @brief PHCON2(PHY Control Register 2)
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*
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*/
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typedef union {
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struct {
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uint32_t reserved_7_0 : 8; // Reserved
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uint32_t hdldis : 1; // Half-Duplex Loopback Disable
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uint32_t reserved_9: 1; // Reserved
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uint32_t jabber: 1; // Disable Jabber Correction
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uint32_t reserved_12_11: 2; // Reserved
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uint32_t txdis: 1; // Disable Twist-Pair Transmitter
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uint32_t frclnk: 1; // Force Linkup
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uint32_t reserved_15: 1; //Reserved
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};
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uint32_t val;
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} phcon2_reg_t;
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#define ETH_PHY_PHCON2_REG_ADDR (0x10)
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/**
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* @brief PHSTAT2(PHY Status Register 2)
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*
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*/
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typedef union {
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struct {
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uint32_t reserved_4_0 : 5; // Reserved
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uint32_t plrity : 1; // Polarity Status
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uint32_t reserved_8_6 : 3; // Reserved
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uint32_t dpxstat : 1; // PHY Duplex Status
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uint32_t lstat : 1; // PHY Link Status (non-latching)
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uint32_t colstat : 1; // PHY Collision Status
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uint32_t rxstat : 1; // PHY Receive Status
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uint32_t txstat : 1; // PHY Transmit Status
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uint32_t reserved_15_14 : 2; // Reserved
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};
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uint32_t val;
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} phstat2_reg_t;
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#define ETH_PHY_PHSTAT2_REG_ADDR (0x11)
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typedef struct {
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esp_eth_phy_t parent;
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esp_eth_mediator_t *eth;
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uint32_t addr;
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uint32_t reset_timeout_ms;
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eth_link_t link_status;
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int reset_gpio_num;
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} phy_enc28j60_t;
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static esp_err_t enc28j60_update_link_duplex_speed(phy_enc28j60_t *enc28j60)
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{
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esp_eth_mediator_t *eth = enc28j60->eth;
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eth_speed_t speed = ETH_SPEED_10M; // enc28j60 speed is fixed to 10Mbps
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eth_duplex_t duplex = ETH_DUPLEX_HALF;
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phstat2_reg_t phstat;
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PHY_CHECK(eth->phy_reg_read(eth, enc28j60->addr, ETH_PHY_PHSTAT2_REG_ADDR, &(phstat.val)) == ESP_OK,
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"read PHSTAT2 failed", err);
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eth_link_t link = phstat.lstat ? ETH_LINK_UP : ETH_LINK_DOWN;
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/* check if link status changed */
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if (enc28j60->link_status != link) {
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/* when link up, read result */
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if (link == ETH_LINK_UP) {
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if (phstat.dpxstat) {
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duplex = ETH_DUPLEX_FULL;
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} else {
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duplex = ETH_DUPLEX_HALF;
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}
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PHY_CHECK(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed) == ESP_OK,
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"change speed failed", err);
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PHY_CHECK(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex) == ESP_OK,
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"change duplex failed", err);
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}
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PHY_CHECK(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link) == ESP_OK,
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"change link failed", err);
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enc28j60->link_status = link;
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}
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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static esp_err_t enc28j60_set_mediator(esp_eth_phy_t *phy, esp_eth_mediator_t *eth)
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{
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PHY_CHECK(eth, "can't set mediator for enc28j60 to null", err);
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phy_enc28j60_t *enc28j60 = __containerof(phy, phy_enc28j60_t, parent);
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enc28j60->eth = eth;
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return ESP_OK;
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err:
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return ESP_ERR_INVALID_ARG;
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}
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static esp_err_t enc28j60_get_link(esp_eth_phy_t *phy)
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{
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phy_enc28j60_t *enc28j60 = __containerof(phy, phy_enc28j60_t, parent);
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/* Updata information about link, speed, duplex */
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PHY_CHECK(enc28j60_update_link_duplex_speed(enc28j60) == ESP_OK, "update link duplex speed failed", err);
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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static esp_err_t enc28j60_reset(esp_eth_phy_t *phy)
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{
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phy_enc28j60_t *enc28j60 = __containerof(phy, phy_enc28j60_t, parent);
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enc28j60->link_status = ETH_LINK_DOWN;
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esp_eth_mediator_t *eth = enc28j60->eth;
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bmcr_reg_t bmcr = {.reset = 1};
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PHY_CHECK(eth->phy_reg_write(eth, enc28j60->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val) == ESP_OK,
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"write BMCR failed", err);
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/* Wait for reset complete */
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uint32_t to = 0;
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for (to = 0; to < enc28j60->reset_timeout_ms / 10; to++) {
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vTaskDelay(pdMS_TO_TICKS(10));
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PHY_CHECK(eth->phy_reg_read(eth, enc28j60->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)) == ESP_OK,
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"read BMCR failed", err);
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if (!bmcr.reset) {
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break;
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}
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}
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PHY_CHECK(to < enc28j60->reset_timeout_ms / 10, "PHY reset timeout", err);
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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static esp_err_t enc28j60_reset_hw(esp_eth_phy_t *phy)
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{
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phy_enc28j60_t *enc28j60 = __containerof(phy, phy_enc28j60_t, parent);
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// set reset_gpio_num minus zero can skip hardware reset phy chip
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if (enc28j60->reset_gpio_num >= 0) {
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gpio_pad_select_gpio(enc28j60->reset_gpio_num);
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gpio_set_direction(enc28j60->reset_gpio_num, GPIO_MODE_OUTPUT);
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gpio_set_level(enc28j60->reset_gpio_num, 0);
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gpio_set_level(enc28j60->reset_gpio_num, 1);
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}
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return ESP_OK;
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}
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static esp_err_t enc28j60_negotiate(esp_eth_phy_t *phy)
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{
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/**
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* ENC28J60 does not support automatic duplex negotiation.
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* If it is connected to an automatic duplex negotiation enabled network switch,
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* ENC28J60 will be detected as a half-duplex device.
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* To communicate in Full-Duplex mode, ENC28J60 and the remote node
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* must be manually configured for full-duplex operation.
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*/
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phy_enc28j60_t *enc28j60 = __containerof(phy, phy_enc28j60_t, parent);
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/* Updata information about link, speed, duplex */
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PHY_CHECK(enc28j60_update_link_duplex_speed(enc28j60) == ESP_OK, "update link duplex speed failed", err);
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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static esp_err_t enc28j60_pwrctl(esp_eth_phy_t *phy, bool enable)
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{
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phy_enc28j60_t *enc28j60 = __containerof(phy, phy_enc28j60_t, parent);
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esp_eth_mediator_t *eth = enc28j60->eth;
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bmcr_reg_t bmcr;
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PHY_CHECK(eth->phy_reg_read(eth, enc28j60->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)) == ESP_OK,
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"read BMCR failed", err);
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if (!enable) {
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/* Enable IEEE Power Down Mode */
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bmcr.power_down = 1;
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} else {
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/* Disable IEEE Power Down Mode */
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bmcr.power_down = 0;
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}
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PHY_CHECK(eth->phy_reg_write(eth, enc28j60->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val) == ESP_OK,
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"write BMCR failed", err);
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PHY_CHECK(eth->phy_reg_read(eth, enc28j60->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)) == ESP_OK,
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"read BMCR failed", err);
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if (!enable) {
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PHY_CHECK(bmcr.power_down == 1, "power down failed", err);
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} else {
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PHY_CHECK(bmcr.power_down == 0, "power up failed", err);
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}
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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static esp_err_t enc28j60_set_addr(esp_eth_phy_t *phy, uint32_t addr)
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{
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phy_enc28j60_t *enc28j60 = __containerof(phy, phy_enc28j60_t, parent);
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enc28j60->addr = addr;
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return ESP_OK;
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}
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static esp_err_t enc28j60_get_addr(esp_eth_phy_t *phy, uint32_t *addr)
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{
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PHY_CHECK(addr, "addr can't be null", err);
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phy_enc28j60_t *enc28j60 = __containerof(phy, phy_enc28j60_t, parent);
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*addr = enc28j60->addr;
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return ESP_OK;
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err:
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return ESP_ERR_INVALID_ARG;
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}
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static esp_err_t enc28j60_del(esp_eth_phy_t *phy)
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{
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phy_enc28j60_t *enc28j60 = __containerof(phy, phy_enc28j60_t, parent);
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free(enc28j60);
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return ESP_OK;
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}
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static esp_err_t enc28j60_init(esp_eth_phy_t *phy)
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{
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phy_enc28j60_t *enc28j60 = __containerof(phy, phy_enc28j60_t, parent);
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esp_eth_mediator_t *eth = enc28j60->eth;
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/* Power on Ethernet PHY */
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PHY_CHECK(enc28j60_pwrctl(phy, true) == ESP_OK, "power control failed", err);
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/* Reset Ethernet PHY */
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PHY_CHECK(enc28j60_reset(phy) == ESP_OK, "reset failed", err);
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/* Check PHY ID */
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phyidr1_reg_t id1;
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phyidr2_reg_t id2;
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PHY_CHECK(eth->phy_reg_read(eth, enc28j60->addr, ETH_PHY_IDR1_REG_ADDR, &(id1.val)) == ESP_OK,
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"read ID1 failed", err);
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PHY_CHECK(eth->phy_reg_read(eth, enc28j60->addr, ETH_PHY_IDR2_REG_ADDR, &(id2.val)) == ESP_OK,
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"read ID2 failed", err);
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PHY_CHECK(id1.oui_msb == 0x0083 && id2.oui_lsb == 0x05 && id2.vendor_model == 0x00,
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"wrong chip ID", err);
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/* Disable half duplex loopback */
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phcon2_reg_t phcon2;
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PHY_CHECK(eth->phy_reg_read(eth, enc28j60->addr, ETH_PHY_PHCON2_REG_ADDR, &(phcon2.val)) == ESP_OK,
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"read PHCON2 failed", err);
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phcon2.hdldis = 1;
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PHY_CHECK(eth->phy_reg_write(eth, enc28j60->addr, ETH_PHY_PHCON2_REG_ADDR, phcon2.val) == ESP_OK,
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"write PHCON2 failed", err);
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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static esp_err_t enc28j60_deinit(esp_eth_phy_t *phy)
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{
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/* Power off Ethernet PHY */
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PHY_CHECK(enc28j60_pwrctl(phy, false) == ESP_OK, "power off Ethernet PHY failed", err);
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return ESP_OK;
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err:
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return ESP_FAIL;
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}
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esp_eth_phy_t *esp_eth_phy_new_enc28j60(const eth_phy_config_t *config)
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{
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PHY_CHECK(config, "can't set phy config to null", err);
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phy_enc28j60_t *enc28j60 = calloc(1, sizeof(phy_enc28j60_t));
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PHY_CHECK(enc28j60, "calloc enc28j60 failed", err);
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enc28j60->addr = config->phy_addr; // although PHY addr is meaningless to ENC28J60
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enc28j60->reset_timeout_ms = config->reset_timeout_ms;
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enc28j60->reset_gpio_num = config->reset_gpio_num;
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enc28j60->link_status = ETH_LINK_DOWN;
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enc28j60->parent.reset = enc28j60_reset;
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enc28j60->parent.reset_hw = enc28j60_reset_hw;
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enc28j60->parent.init = enc28j60_init;
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enc28j60->parent.deinit = enc28j60_deinit;
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enc28j60->parent.set_mediator = enc28j60_set_mediator;
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enc28j60->parent.negotiate = enc28j60_negotiate;
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enc28j60->parent.get_link = enc28j60_get_link;
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enc28j60->parent.pwrctl = enc28j60_pwrctl;
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enc28j60->parent.get_addr = enc28j60_get_addr;
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enc28j60->parent.set_addr = enc28j60_set_addr;
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enc28j60->parent.del = enc28j60_del;
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return &(enc28j60->parent);
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err:
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return NULL;
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}
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