175 lines
4.2 KiB
C
175 lines
4.2 KiB
C
#include <stdlib.h>
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#include <stdint.h>
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#include "esp_timer.h"
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#include "esp_log.h"
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#include "esp_attr.h"
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#include "ccomp_timer.h"
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#include "eri.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/clk.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/clk.h"
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#endif
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#include "unity.h"
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#include "sdkconfig.h"
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static const char* TAG = "test_ccomp_timer";
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#if CONFIG_IDF_TARGET_ESP32
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#define CACHE_WAYS 2
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#define CACHE_LINE_SIZE 32
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#define CACHE_SIZE (1 << 15)
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// Only test half due to lack of memory
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#define TEST_SIZE (CACHE_SIZE / 2)
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#elif CONFIG_IDF_TARGET_ESP32S2
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// Default cache configuration - no override specified on
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// test_utils config
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#define CACHE_WAYS 8
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#define CACHE_LINE_SIZE 32
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#define CACHE_SIZE (1 << 13)
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#define TEST_SIZE (CACHE_SIZE)
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#endif
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typedef struct {
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uint8_t **accesses;
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size_t len;
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} ccomp_test_access_t;
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typedef struct {
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int64_t wall;
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int64_t ccomp;
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} ccomp_test_time_t;
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#if CONFIG_ESP32_SPIRAM_SUPPORT
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static uint8_t *flash_mem;
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#else
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static const uint8_t flash_mem[2 * CACHE_SIZE] = {0};
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#endif
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static IRAM_ATTR void perform_accesses(ccomp_test_access_t *access)
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{
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volatile int a = 0;
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for (int i = 0; i < access->len; i++) {
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a += (int)(*(access->accesses[i]));
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}
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}
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static void prepare_cache(const uint8_t *to_cache)
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{
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volatile int a = 0;
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for (int i = 0; i < CACHE_SIZE; i++) {
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a += to_cache[i];
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}
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}
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static void prepare_access_pattern(int hit_rate, const uint8_t *cached, ccomp_test_access_t *out)
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{
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assert(hit_rate <= 100);
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assert(hit_rate >= 0);
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int misses = (100 - hit_rate) * CACHE_LINE_SIZE;
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int hits = hit_rate * CACHE_LINE_SIZE;
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uint8_t **accesses = calloc(TEST_SIZE, sizeof(uint8_t *));
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for (int i = 0, h = 0, i_h = 1, m = -1, i_m = 0; i < TEST_SIZE; i++, h += i_h, m += i_m) {
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if (i_m) {
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accesses[i] = (uint8_t*) (cached + CACHE_SIZE + i);
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}
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else {
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accesses[i] = (uint8_t*) (cached + i);
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}
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if (h >= hits) {
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h = -1;
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i_h = 0;
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m = 0;
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i_m = 1;
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}
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if (m >= misses) {
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m = -1;
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i_m = 0;
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h = 0;
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i_h = 1;
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}
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}
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out->accesses = accesses;
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out->len = TEST_SIZE;
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}
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static ccomp_test_time_t perform_test_at_hit_rate(int hit_rate, const uint8_t *mem)
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{
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ccomp_test_access_t access;
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prepare_access_pattern(hit_rate, mem, &access);
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prepare_cache(mem);
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int64_t start = esp_timer_get_time();
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ccomp_timer_start();
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perform_accesses(&access);
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ccomp_test_time_t t = {
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.ccomp = ccomp_timer_stop(),
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.wall = esp_timer_get_time() - start
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};
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free(access.accesses);
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return t;
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}
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static ccomp_test_time_t ccomp_test_ref_time(void)
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{
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#if CONFIG_ESP32_SPIRAM_SUPPORT
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uint8_t *mem = heap_caps_malloc(2 * CACHE_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT);
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#else
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uint8_t *mem = heap_caps_malloc(sizeof(flash_mem), MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT);
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#endif
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ccomp_test_time_t t = perform_test_at_hit_rate(0, mem);
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free(mem);
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return t;
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}
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TEST_CASE("data cache hit rate sweep", "[test_utils][ccomp_timer]")
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{
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ccomp_test_time_t t_ref;
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ccomp_test_time_t t_hr;
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#if CONFIG_ESP32_SPIRAM_SUPPORT
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flash_mem = heap_caps_malloc(2 * CACHE_SIZE, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM);
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#endif
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// Perform accesses on RAM. The time recorded here serves as
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// reference.
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t_ref = ccomp_test_ref_time();
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ESP_LOGI(TAG, "Reference Time(us): %lld", (long long)t_ref.ccomp);
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// Measure time at particular hit rates
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for (int i = 0; i <= 100; i += 5)
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{
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t_hr = perform_test_at_hit_rate(i, flash_mem);
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float error = (abs(t_ref.ccomp - t_hr.ccomp) / (float)t_ref.ccomp) * 100.0f;
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ESP_LOGI(TAG, "Hit Rate(%%): %d Wall Time(us): %lld Compensated Time(us): %lld Error(%%): %f", i, (long long)t_hr.wall, (long long)t_hr.ccomp, error);
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// Check if the measured time is at least within some percent of the
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// reference.
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TEST_ASSERT(error <= 5.0f);
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}
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#if CONFIG_ESP32_SPIRAM_SUPPORT
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free(flash_mem);
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#endif
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}
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