7a527896dc
Starting the ULP using SENS_SAR_START_FORCE_REG doesn’t disable clock gating of RTC fast clock. When SoC goes into deep sleep mode, RTC fast clock gets gated, so ULP can no longer run. Instead, it has to be started using the timer (RTC_CNTL_ULP_CP_SLP_TIMER_EN bit). When ULP is enabled by the timer, clock also gets enabled.
278 lines
9.6 KiB
C
278 lines
9.6 KiB
C
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp32/ulp.h"
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#include "soc/soc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/sens_reg.h"
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#include "sdkconfig.h"
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static const char* TAG = "ulp";
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typedef struct {
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uint32_t label : 16;
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uint32_t addr : 11;
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uint32_t unused : 1;
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uint32_t type : 4;
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} reloc_info_t;
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#define RELOC_TYPE_LABEL 0
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#define RELOC_TYPE_BRANCH 1
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/* This record means: there is a label at address
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* insn_addr, with number label_num.
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*/
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#define RELOC_INFO_LABEL(label_num, insn_addr) (reloc_info_t) { \
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.label = label_num, \
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.addr = insn_addr, \
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.unused = 0, \
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.type = RELOC_TYPE_LABEL }
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/* This record means: there is a branch instruction at
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* insn_addr, it needs to be changed to point to address
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* of label label_num.
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*/
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#define RELOC_INFO_BRANCH(label_num, insn_addr) (reloc_info_t) { \
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.label = label_num, \
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.addr = insn_addr, \
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.unused = 0, \
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.type = RELOC_TYPE_BRANCH }
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/* Processing branch and label macros involves four steps:
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*
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* 1. Iterate over program and count all instructions
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* with "macro" opcode. Allocate relocations array
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* with number of entries equal to number of macro
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* instructions.
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*
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* 2. Remove all fake instructions with "macro" opcode
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* and record their locations into relocations array.
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* Removal is done using two pointers. Instructions
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* are read from read_ptr, and written to write_ptr.
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* When a macro instruction is encountered,
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* its contents are recorded into the appropriate
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* table, and then read_ptr is advanced again.
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* When a real instruction is encountered, it is
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* read via read_ptr and written to write_ptr.
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* In the end, all macro instructions are removed,
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* size of the program (expressed in words) is
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* reduced by the total number of macro instructions
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* which were present.
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*
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* 3. Sort relocations array by label number, and then
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* by type ("label" or "branch") if label numbers
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* match. This is done to simplify lookup on the next
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* step.
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*
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* 4. Iterate over entries of relocations table.
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* For each label number, label entry comes first
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* because the array was sorted at the previous step.
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* Label address is recorded, and all subsequent
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* "branch" entries which point to the same label number
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* are processed. For each branch entry, correct offset
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* or absolute address is calculated, depending on branch
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* type, and written into the appropriate field of
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* the instruction.
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*
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*/
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static esp_err_t do_single_reloc(ulp_insn_t* program, uint32_t load_addr,
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reloc_info_t label_info, reloc_info_t branch_info)
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{
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size_t insn_offset = branch_info.addr - load_addr;
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ulp_insn_t* insn = &program[insn_offset];
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// B and BX have the same layout of opcode/sub_opcode fields,
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// and share the same opcode
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assert(insn->b.opcode == OPCODE_BRANCH
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&& "branch macro was applied to a non-branch instruction");
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switch (insn->b.sub_opcode) {
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case SUB_OPCODE_B: {
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int32_t offset = ((int32_t) label_info.addr) - ((int32_t) branch_info.addr);
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uint32_t abs_offset = abs(offset);
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uint32_t sign = (offset >= 0) ? 0 : 1;
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if (abs_offset > 127) {
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ESP_LOGW(TAG, "target out of range: branch from %x to %x",
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branch_info.addr, label_info.addr);
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return ESP_ERR_ULP_BRANCH_OUT_OF_RANGE;
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}
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insn->b.offset = abs_offset;
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insn->b.sign = sign;
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break;
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}
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case SUB_OPCODE_BX: {
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assert(insn->bx.reg == 0 &&
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"relocation applied to a jump with offset in register");
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insn->bx.addr = label_info.addr;
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break;
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}
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default:
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assert(false && "unexpected sub-opcode");
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}
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return ESP_OK;
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}
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esp_err_t ulp_process_macros_and_load(uint32_t load_addr, const ulp_insn_t* program, size_t* psize)
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{
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const ulp_insn_t* read_ptr = program;
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const ulp_insn_t* end = program + *psize;
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size_t macro_count = 0;
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// step 1: calculate number of macros
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while (read_ptr < end) {
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ulp_insn_t r_insn = *read_ptr;
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if (r_insn.macro.opcode == OPCODE_MACRO) {
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++macro_count;
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}
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++read_ptr;
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}
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size_t real_program_size = *psize - macro_count;
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const size_t ulp_mem_end = CONFIG_ULP_COPROC_RESERVE_MEM / sizeof(ulp_insn_t);
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if (load_addr > ulp_mem_end) {
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ESP_LOGW(TAG, "invalid load address %x, max is %x",
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load_addr, ulp_mem_end);
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return ESP_ERR_ULP_INVALID_LOAD_ADDR;
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}
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if (real_program_size + load_addr > ulp_mem_end) {
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ESP_LOGE(TAG, "program too big: %d words, max is %d words",
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real_program_size, ulp_mem_end);
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return ESP_ERR_ULP_SIZE_TOO_BIG;
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}
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// If no macros found, copy the program and return.
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if (macro_count == 0) {
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memcpy(((ulp_insn_t*) RTC_SLOW_MEM) + load_addr, program, *psize * sizeof(ulp_insn_t));
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return ESP_OK;
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}
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reloc_info_t* reloc_info =
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(reloc_info_t*) malloc(sizeof(reloc_info_t) * macro_count);
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if (reloc_info == NULL) {
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return ESP_ERR_NO_MEM;
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}
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// step 2: record macros into reloc_info array
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// and remove them from then program
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read_ptr = program;
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ulp_insn_t* output_program = ((ulp_insn_t*) RTC_SLOW_MEM) + load_addr;
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ulp_insn_t* write_ptr = output_program;
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uint32_t cur_insn_addr = load_addr;
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reloc_info_t* cur_reloc = reloc_info;
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while (read_ptr < end) {
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ulp_insn_t r_insn = *read_ptr;
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if (r_insn.macro.opcode == OPCODE_MACRO) {
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switch(r_insn.macro.sub_opcode) {
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case SUB_OPCODE_MACRO_LABEL:
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*cur_reloc = RELOC_INFO_LABEL(r_insn.macro.label,
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cur_insn_addr);
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break;
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case SUB_OPCODE_MACRO_BRANCH:
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*cur_reloc = RELOC_INFO_BRANCH(r_insn.macro.label,
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cur_insn_addr);
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break;
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default:
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assert(0 && "invalid sub_opcode for macro insn");
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}
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++read_ptr;
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assert(read_ptr != end && "program can not end with macro insn");
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++cur_reloc;
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} else {
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// normal instruction (not a macro)
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*write_ptr = *read_ptr;
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++read_ptr;
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++write_ptr;
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++cur_insn_addr;
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}
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}
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// step 3: sort relocations array
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int reloc_sort_func(const void* p_lhs, const void* p_rhs) {
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const reloc_info_t lhs = *(const reloc_info_t*) p_lhs;
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const reloc_info_t rhs = *(const reloc_info_t*) p_rhs;
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if (lhs.label < rhs.label) {
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return -1;
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} else if (lhs.label > rhs.label) {
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return 1;
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}
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// label numbers are equal
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if (lhs.type < rhs.type) {
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return -1;
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} else if (lhs.type > rhs.type) {
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return 1;
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}
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// both label number and type are equal
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return 0;
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}
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qsort(reloc_info, macro_count, sizeof(reloc_info_t),
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reloc_sort_func);
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// step 4: walk relocations array and fix instructions
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reloc_info_t* reloc_end = reloc_info + macro_count;
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cur_reloc = reloc_info;
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while(cur_reloc < reloc_end) {
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reloc_info_t label_info = *cur_reloc;
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assert(label_info.type == RELOC_TYPE_LABEL);
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++cur_reloc;
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while (cur_reloc < reloc_end) {
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if (cur_reloc->type == RELOC_TYPE_LABEL) {
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if(cur_reloc->label == label_info.label) {
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ESP_LOGE(TAG, "duplicate label definition: %d",
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label_info.label);
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free(reloc_info);
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return ESP_ERR_ULP_DUPLICATE_LABEL;
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}
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break;
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}
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if (cur_reloc->label != label_info.label) {
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ESP_LOGE(TAG, "branch to an inexistent label: %d",
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cur_reloc->label);
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free(reloc_info);
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return ESP_ERR_ULP_UNDEFINED_LABEL;
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}
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esp_err_t rc = do_single_reloc(output_program, load_addr,
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label_info, *cur_reloc);
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if (rc != ESP_OK) {
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free(reloc_info);
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return rc;
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}
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++cur_reloc;
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}
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}
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free(reloc_info);
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*psize = real_program_size;
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return ESP_OK;
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}
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esp_err_t ulp_run(uint32_t entry_point)
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{
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// disable ULP timer
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CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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// set entry point
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SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_PC_INIT_V, entry_point, SENS_PC_INIT_S);
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// disable force start
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP_M);
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// make sure voltage is raised when RTC 8MCLK is enabled
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FOLW_8M);
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// enable ULP timer
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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return ESP_OK;
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}
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