116 lines
4.8 KiB
C
116 lines
4.8 KiB
C
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include "rom/ets_sys.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/timer_group_reg.h"
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#define MHZ (1000000)
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/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
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* This feature counts the number of XTAL clock cycles within a given number of
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* RTC_SLOW_CLK cycles.
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*
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* Slow clock calibration feature has two modes of operation: one-off and cycling.
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* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
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* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
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* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
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* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
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* enabled using TIMG_RTC_CALI_START bit.
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*/
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uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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{
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rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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/* Enable requested clock (150k clock is always on) */
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if (cal_clk == RTC_CAL_32K_XTAL) {
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
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}
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if (cal_clk == RTC_CAL_8MD256) {
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
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}
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/* Prepare calibration */
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
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/* Figure out how long to wait for calibration to finish */
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uint32_t expected_freq;
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rtc_slow_freq_t slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
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if (cal_clk == RTC_CAL_32K_XTAL ||
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(cal_clk == RTC_CAL_RTC_MUX && slow_freq == RTC_SLOW_FREQ_32K_XTAL)) {
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expected_freq = 32768; /* standard 32k XTAL */
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} else if (cal_clk == RTC_CAL_8MD256 ||
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(cal_clk == RTC_CAL_RTC_MUX && slow_freq == RTC_SLOW_FREQ_8MD256)) {
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expected_freq = 8 * MHZ / 256;
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} else {
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expected_freq = 150000; /* 150k internal oscillator */
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}
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uint32_t us_time_estimate = slowclk_cycles * MHZ / expected_freq;
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/* Start calibration */
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
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SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
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/* Wait the expected time calibration should take.
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* TODO: if running under RTOS, and us_time_estimate > RTOS tick, use the
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* RTOS delay function.
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*/
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ets_delay_us(us_time_estimate);
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/* Wait for calibration to finish up to another us_time_estimate */
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int timeout_us = us_time_estimate;
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while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) &&
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timeout_us-- > 0) {
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ets_delay_us(1);
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}
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if (cal_clk == RTC_CAL_32K_XTAL) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
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}
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if (cal_clk == RTC_CAL_8MD256) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
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}
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if (timeout_us == 0) {
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/* timed out waiting for calibration */
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return 0;
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}
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uint64_t xtal_cycles = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
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uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
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uint64_t period_64 = (xtal_cycles << RTC_CLK_CAL_FRACT) / divider;
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uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
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return period;
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}
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uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
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{
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/* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
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* TODO: fix overflow.
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*/
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return (time_in_us << RTC_CLK_CAL_FRACT) / period;
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}
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uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
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{
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return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
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}
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uint64_t rtc_time_get()
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{
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SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
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while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) {
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ets_delay_us(1); // might take 1 RTC slowclk period, don't flood RTC bus
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}
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SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR);
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uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
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t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
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return t;
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}
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