551 lines
22 KiB
C
551 lines
22 KiB
C
/*
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Driver bits for PSRAM chips (at the moment only the ESP-PSRAM32 chip).
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*/
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// Copyright 2013-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#include "string.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_types.h"
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#include "esp_log.h"
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#include "spiram_psram.h"
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#include "esp32s2/rom/ets_sys.h"
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#include "esp32s2/rom/spi_flash.h"
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#include "esp32s2/rom/opi_flash.h"
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#include "esp32s2/rom/gpio.h"
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#include "esp32s2/rom/cache.h"
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#include "esp32s2/rom/efuse.h"
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#include "soc/dport_reg.h"
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#include "soc/efuse_periph.h"
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#include "soc/spi_caps.h"
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#include "soc/io_mux_reg.h"
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#include "soc/apb_ctrl_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/efuse_reg.h"
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#include "soc/soc.h"
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#include "driver/gpio.h"
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#include "driver/spi_common_internal.h"
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#include "driver/spi_common.h"
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#include "driver/periph_ctrl.h"
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#include "bootloader_common.h"
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#if CONFIG_SPIRAM
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#include "soc/rtc.h"
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static const char* TAG = "psram";
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//Commands for PSRAM chip
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#define PSRAM_READ 0x03
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#define PSRAM_FAST_READ 0x0B
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#define PSRAM_FAST_READ_DUMMY 0x3
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#define PSRAM_FAST_READ_QUAD 0xEB
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#define PSRAM_FAST_READ_QUAD_DUMMY 0x5
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#define PSRAM_WRITE 0x02
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#define PSRAM_QUAD_WRITE 0x38
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#define PSRAM_ENTER_QMODE 0x35
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#define PSRAM_EXIT_QMODE 0xF5
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#define PSRAM_RESET_EN 0x66
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#define PSRAM_RESET 0x99
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#define PSRAM_SET_BURST_LEN 0xC0
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#define PSRAM_DEVICE_ID 0x9F
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// ID
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#define PSRAM_ID_KGD_M 0xff
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#define PSRAM_ID_KGD_S 8
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#define PSRAM_ID_KGD 0x5d
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#define PSRAM_ID_EID_M 0xff
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#define PSRAM_ID_EID_S 16
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// Use the [7:5](bit7~bit5) of EID to distinguish the psram size:
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//
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// BIT7 | BIT6 | BIT5 | SIZE(MBIT)
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// -------------------------------------
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// 0 | 0 | 0 | 16
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// 0 | 0 | 1 | 32
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// 0 | 1 | 0 | 64
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#define PSRAM_EID_SIZE_M 0x07
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#define PSRAM_EID_SIZE_S 5
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#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
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#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
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#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M)
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#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD)
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// For the old version 32Mbit psram, using the spicial driver */
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#define PSRAM_IS_32MBIT_VER0(id) (PSRAM_EID(id) == 0x20)
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#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26)
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// IO-pins for PSRAM.
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// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
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// hardcode the flash pins as well, making this code incompatible with either a setup
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// that has the flash on non-standard pins or ESP32s with built-in flash.
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#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
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#define FLASH_CS_IO SPI_CS0_GPIO_NUM
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// PSRAM clock and cs IO should be configured based on hardware design.
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#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30
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#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26
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#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
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#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
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#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM
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#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM
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#define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M
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#define CS_FLASH_SEL SPI_MEM_CS0_DIS_M
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#define PSRAM_IO_MATRIX_DUMMY_20M 0
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#define PSRAM_IO_MATRIX_DUMMY_40M 0
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#define PSRAM_IO_MATRIX_DUMMY_80M 0
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#define _SPI_CACHE_PORT 0
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#define _SPI_FLASH_PORT 1
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#define _SPI_80M_CLK_DIV 1
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#define _SPI_40M_CLK_DIV 2
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#define _SPI_20M_CLK_DIV 4
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typedef enum {
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PSRAM_CLK_MODE_NORM = 0, /*!< Normal SPI mode */
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PSRAM_CLK_MODE_A1C, /*!< ONE extra clock cycles after CS is set high level */
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PSRAM_CLK_MODE_A2C, /*!< Two extra clock cycles after CS is set high level */
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PSRAM_CLK_MODE_ALON, /*!< clock always on */
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PSRAM_CLK_MODE_MAX,
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} psram_clk_mode_t;
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typedef enum {
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PSRAM_EID_SIZE_16MBITS = 0,
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PSRAM_EID_SIZE_32MBITS = 1,
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PSRAM_EID_SIZE_64MBITS = 2,
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} psram_eid_size_t;
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typedef struct {
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uint8_t flash_clk_io;
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uint8_t flash_cs_io;
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uint8_t psram_clk_io;
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uint8_t psram_cs_io;
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uint8_t psram_spiq_sd0_io;
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uint8_t psram_spid_sd1_io;
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uint8_t psram_spiwp_sd3_io;
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uint8_t psram_spihd_sd2_io;
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} psram_io_t;
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#define PSRAM_IO_CONF_DEFAULT() { \
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.flash_clk_io = FLASH_CLK_IO, \
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.flash_cs_io = FLASH_CS_IO, \
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.psram_clk_io = PSRAM_CLK_IO, \
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.psram_cs_io = PSRAM_CS_IO, \
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.psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO, \
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.psram_spid_sd1_io = PSRAM_SPID_SD1_IO, \
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.psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO, \
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.psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO, \
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}
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typedef enum {
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PSRAM_SPI_1 = 0x1,
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/* PSRAM_SPI_2, */
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/* PSRAM_SPI_3, */
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PSRAM_SPI_MAX ,
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} psram_spi_num_t;
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typedef enum {
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PSRAM_CMD_QPI,
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PSRAM_CMD_SPI,
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} psram_cmd_mode_t;
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typedef esp_rom_spi_cmd_t psram_cmd_t;
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static uint32_t s_psram_id = 0;
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static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
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extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
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static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
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{
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if (mode == PSRAM_CMD_QPI) {
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esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE);
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SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M);
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} else if (mode == PSRAM_CMD_SPI) {
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esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE);
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}
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}
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static void _psram_exec_cmd(int spi_num,
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uint32_t cmd, int cmd_bit_len,
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uint32_t addr, int addr_bit_len,
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int dummy_bits,
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uint8_t* mosi_data, int mosi_bit_len,
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uint8_t* miso_data, int miso_bit_len)
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{
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esp_rom_spi_cmd_t conf;
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uint32_t _addr = addr;
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conf.addr = &_addr;
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conf.addrBitLen = addr_bit_len;
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conf.cmd = cmd;
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conf.cmdBitLen = cmd_bit_len;
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conf.dummyBitLen = dummy_bits; // There is a hardware approach on chip723
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conf.txData = (uint32_t*) mosi_data;
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conf.txDataBitLen = mosi_bit_len;
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conf.rxData = (uint32_t*) miso_data;
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conf.rxDataBitLen = miso_bit_len;
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esp_rom_spi_cmd_config(spi_num, &conf);
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}
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void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
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uint32_t cmd, int cmd_bit_len,
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uint32_t addr, int addr_bit_len,
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int dummy_bits,
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uint8_t* mosi_data, int mosi_bit_len,
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uint8_t* miso_data, int miso_bit_len,
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uint32_t cs_mask,
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bool is_write_erase_operation)
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{
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uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num));
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uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num));
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uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num));
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uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num));
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psram_set_op_mode(spi_num, mode);
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_psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len,
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dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
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esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation);
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WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr);
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WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1);
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WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2);
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WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl);
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}
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//exit QPI mode(set back to SPI mode)
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static void psram_disable_qio_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_CMD_QPI,
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PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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//switch psram burst length(32 bytes or 1024 bytes)
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//datasheet says it should be 1024 bytes by default
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static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode)
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{
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psram_exec_cmd(spi_num, mode,
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PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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//send reset command to psram, in spi mode
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static void psram_reset_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
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PSRAM_RESET_EN, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
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PSRAM_RESET, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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esp_err_t psram_enable_wrap(uint32_t wrap_size)
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{
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static int current_wrap_size = 0;
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if (current_wrap_size == wrap_size) {
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return ESP_OK;
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}
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switch (wrap_size) {
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case 32:
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case 0:
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psram_set_wrap_burst_length(PSRAM_SPI_1, PSRAM_CMD_QPI);
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current_wrap_size = wrap_size;
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return ESP_OK;
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case 16:
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case 64:
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default:
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return ESP_FAIL;
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}
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}
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bool psram_support_wrap_size(uint32_t wrap_size)
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{
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switch (wrap_size) {
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case 0:
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case 32:
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return true;
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case 16:
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case 64:
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default:
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return false;
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}
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}
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//read psram id
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static void psram_read_id(uint32_t* dev_id)
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{
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int spi_num = PSRAM_SPI_1;
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psram_disable_qio_mode(spi_num);
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psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
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PSRAM_DEVICE_ID, 8, /* command and command bit len*/
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0, 24, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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(uint8_t*) dev_id, 24, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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//enter QPI mode
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static void IRAM_ATTR psram_enable_qio_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
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PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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static void psram_set_spi1_cmd_cs_timing(psram_clk_mode_t clk_mode)
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{
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if (clk_mode == PSRAM_CLK_MODE_NORM) {
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// SPI1 Flash Operation port
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
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SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
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} else {
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SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
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}
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}
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static void psram_set_spi0_cache_cs_timing(psram_clk_mode_t clk_mode)
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{
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if (clk_mode == PSRAM_CLK_MODE_NORM) {
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// SPI0 SRAM Cache port
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SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 1, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S);
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SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M);
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// SPI0 Flash Cache port
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
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SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
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} else {
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CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
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}
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}
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//psram gpio init , different working frequency we have different solutions
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static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
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{
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psram_io_t psram_io = PSRAM_IO_CONF_DEFAULT();
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
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if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
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/* FLASH pins(except wp / hd) are all configured via IO_MUX in rom. */
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} else {
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// FLASH pins are all configured via GPIO matrix in ROM.
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psram_io.flash_clk_io = EFUSE_SPICONFIG_RET_SPICLK(spiconfig);
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psram_io.flash_cs_io = EFUSE_SPICONFIG_RET_SPICS0(spiconfig);
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psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig);
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psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig);
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psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig);
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psram_io.psram_spiwp_sd3_io = ets_efuse_get_wp_pad();
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}
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#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_FLASHMODE_QOUT
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// WP/HD already configured in bootloader.
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psram_io.psram_spiwp_sd3_io = (psram_io.psram_spiwp_sd3_io <= MAX_PAD_GPIO_NUM ? psram_io.psram_spiwp_sd3_io : CONFIG_BOOTLOADER_SPI_WP_PIN);
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#else
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psram_io.psram_spiwp_sd3_io = (psram_io.psram_spiwp_sd3_io <= MAX_PAD_GPIO_NUM ? psram_io.psram_spiwp_sd3_io : CONFIG_SPIRAM_SPIWP_SD3_PIN);
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esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig);
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#endif
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}
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psram_size_t psram_get_size(void)
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{
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if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
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return PSRAM_SIZE_64MBITS;
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} else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_32MBITS) {
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return PSRAM_SIZE_32MBITS;
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} else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_16MBITS) {
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return PSRAM_SIZE_16MBITS;
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} else {
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return PSRAM_SIZE_MAX;
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}
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return PSRAM_SIZE_MAX;
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}
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//used in UT only
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bool psram_is_32mbit_ver0(void)
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|
{
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return PSRAM_IS_32MBIT_VER0(s_psram_id);
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}
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static void psram_set_clk_mode(int spi_num, psram_clk_mode_t clk_mode)
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{
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if (spi_num == _SPI_CACHE_PORT) {
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REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, clk_mode);
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} else if (spi_num == _SPI_FLASH_PORT) {
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REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, clk_mode);
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}
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}
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|
/*
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* Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA.
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* Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
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*/
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esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init
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|
{
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assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
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// GPIO related settings
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|
psram_gpio_config(mode);
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|
|
|
/* SPI1: set spi1 clk mode, in order to send commands on SPI1 */
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/* SPI1: set cs timing(hold time) in order to send commands on SPI1 */
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psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C);
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psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C);
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|
|
/* 16Mbit psram ID read error
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|
* workaround: Issue a pre-condition of dummy read id, then Read ID command
|
|
*/
|
|
psram_read_id(&s_psram_id);
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|
psram_read_id(&s_psram_id);
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|
if (!PSRAM_IS_VALID(s_psram_id)) {
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|
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id);
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|
return ESP_FAIL;
|
|
}
|
|
|
|
psram_clk_mode_t clk_mode = PSRAM_CLK_MODE_MAX;
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|
if (psram_is_32mbit_ver0()) {
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clk_mode = PSRAM_CLK_MODE_A1C;
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|
// SPI1: keep clock mode and cs timing for spi1
|
|
} else {
|
|
// For other psram, we don't need any extra clock cycles after cs get back to high level
|
|
clk_mode = PSRAM_CLK_MODE_NORM;
|
|
// SPI1: set clock mode and cs timing to normal mode
|
|
psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM);
|
|
psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM);
|
|
}
|
|
|
|
/* SPI1: send psram reset command */
|
|
/* SPI1: send QPI enable command */
|
|
psram_reset_mode(PSRAM_SPI_1);
|
|
psram_enable_qio_mode(PSRAM_SPI_1);
|
|
|
|
// after sending commands, set spi1 clock mode and cs timing to normal mode.
|
|
// since all the operations are sent via SPI0 Cache
|
|
/* SPI1: set clock mode to normal mode. */
|
|
/* SPI1: set cs timing to normal */
|
|
psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM);
|
|
psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM);
|
|
|
|
/* SPI0: set spi0 clock mode */
|
|
/* SPI0: set spi0 flash/cache cs timing */
|
|
psram_set_clk_mode(_SPI_CACHE_PORT, clk_mode);
|
|
psram_set_spi0_cache_cs_timing(clk_mode);
|
|
|
|
// SPI0: init SPI commands for Cache
|
|
psram_cache_init(mode, vaddrmode);
|
|
|
|
return ESP_OK;
|
|
}
|
|
|
|
static void IRAM_ATTR psram_clock_set(int spi_num, int8_t freqdiv)
|
|
{
|
|
uint32_t freqbits;
|
|
if (1 >= freqdiv) {
|
|
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
|
|
} else {
|
|
freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S);
|
|
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
|
|
}
|
|
}
|
|
|
|
//register initialization for sram cache params and r/w commands
|
|
static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode)
|
|
{
|
|
int extra_dummy = 0;
|
|
switch (psram_cache_mode) {
|
|
case PSRAM_CACHE_S80M:
|
|
psram_clock_set(0, 1);
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M;
|
|
break;
|
|
case PSRAM_CACHE_S40M:
|
|
psram_clock_set(0, 2);
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
|
|
break;
|
|
case PSRAM_CACHE_S26M:
|
|
psram_clock_set(0, 3);
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M;
|
|
break;
|
|
case PSRAM_CACHE_S20M:
|
|
psram_clock_set(0, 4);
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M;
|
|
break;
|
|
default:
|
|
psram_clock_set(0, 2);
|
|
break;
|
|
}
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode for cache command
|
|
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode for cache command
|
|
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable cache read command
|
|
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); //enable cache write command
|
|
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S); //write address for cache command.
|
|
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
|
|
|
|
//config sram cache r/w command
|
|
SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
|
|
SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
|
|
SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE,
|
|
SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
|
|
SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
|
|
SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
|
|
SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD,
|
|
SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b
|
|
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
|
|
SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
|
|
|
|
#if !CONFIG_FREERTOS_UNICORE
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT);
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT);
|
|
if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL);
|
|
DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL);
|
|
} else if (vaddrmode == PSRAM_VADDR_MODE_EVENODD) {
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT);
|
|
DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_SPLIT);
|
|
}
|
|
#endif
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
|
|
}
|
|
#endif // CONFIG_SPIRAM
|