This commit updates the watchdog timers (MWDT and RWDT) in the following ways: - Add seprate LL for MWDT and RWDT. - Add a combined WDT HAL for all Watchdog Timers - Update int_wdt.c and task_wdt.c to use WDT HAL - Remove most dependencies on LL or direct register access in other components. They will now use the WDT HAL - Update use of watchdogs (including RTC WDT) in bootloader and startup code to use the HAL layer.
318 lines
13 KiB
C
318 lines
13 KiB
C
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <sys/cdefs.h>
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#include <sys/time.h>
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp32s2/clk.h"
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#include "esp_clk_internal.h"
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#include "esp32s2/rom/ets_sys.h"
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#include "esp32s2/rom/uart.h"
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#include "esp32s2/rom/rtc.h"
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#include "soc/system_reg.h"
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#include "soc/dport_access.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_periph.h"
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#include "soc/i2s_reg.h"
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#include "hal/wdt_hal.h"
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#include "driver/periph_ctrl.h"
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#include "xtensa/core-macros.h"
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#include "bootloader_clock.h"
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#include "soc/syscon_reg.h"
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/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
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* Larger values increase startup delay. Smaller values may cause false positive
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* detection (i.e. oscillator runs for a few cycles and then stops).
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*/
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#define SLOW_CLK_CAL_CYCLES CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES
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#define MHZ (1000000)
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/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL.
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* The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6.
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*/
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#define MIN_32K_XTAL_CAL_VAL 15000000L
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/* Indicates that this 32k oscillator gets input from external oscillator, rather
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* than a crystal.
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*/
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#define EXT_OSC_FLAG BIT(3)
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/* This is almost the same as rtc_slow_freq_t, except that we define
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* an extra enum member for the external 32k oscillator.
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* For convenience, lower 2 bits should correspond to rtc_slow_freq_t values.
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*/
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typedef enum {
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SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 90 kHz RC oscillator
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SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL
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SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256
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SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
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} slow_clk_sel_t;
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static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
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static const char *TAG = "clk";
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void esp_clk_init(void)
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{
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rtc_config_t cfg = RTC_CONFIG_DEFAULT();
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rtc_init(cfg);
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assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
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rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
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#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
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// WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
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// If the frequency changes from 90kHz to 32kHz, then the timeout set for the WDT will increase 2.8 times.
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// Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
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// This prevents excessive delay before resetting in case the supply voltage is drawdown.
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// (If frequency is changed from 90kHz to 32kHz then WDT timeout will increased to 1.6sec * 90/32 = 4.5 sec).
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wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
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uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_feed(&rtc_wdt_ctx);
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//Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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#if defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS)
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select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
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#elif defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_OSC)
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select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
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#elif defined(CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256)
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select_rtc_slow_clk(SLOW_CLK_8MD256);
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#else
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select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
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#endif
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#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
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// After changing a frequency WDT timeout needs to be set for new frequency.
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stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000ULL);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_feed(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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rtc_cpu_freq_config_t old_config, new_config;
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rtc_clk_cpu_freq_get_config(&old_config);
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const uint32_t old_freq_mhz = old_config.freq_mhz;
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const uint32_t new_freq_mhz = CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ;
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bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
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assert(res);
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// Wait for UART TX to finish, otherwise some UART output will be lost
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// when switching APB frequency
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uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
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rtc_clk_cpu_freq_set_config(&new_config);
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// Re calculate the ccount to make time calculation correct.
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XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * new_freq_mhz / old_freq_mhz );
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}
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int IRAM_ATTR esp_clk_cpu_freq(void)
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{
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return ets_get_cpu_frequency() * 1000000;
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}
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int IRAM_ATTR esp_clk_apb_freq(void)
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{
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return MIN(ets_get_cpu_frequency(), 80) * 1000000;
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}
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static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
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{
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rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
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uint32_t cal_val = 0;
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/* number of times to repeat 32k XTAL calibration
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* before giving up and switching to the internal RC
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*/
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#ifdef CONFIG_IDF_TARGET_ESP32
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int retry_32k_xtal = 1; /* don't change the behavior for the ESP32 */
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#else
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int retry_32k_xtal = 3;
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#endif
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do {
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if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
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/* 32k XTAL oscillator needs to be enabled and running before it can
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* be used. Hardware doesn't have a direct way of checking if the
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* oscillator is running. Here we use rtc_clk_cal function to count
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* the number of main XTAL cycles in the given number of 32k XTAL
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* oscillator cycles. If the 32k XTAL has not started up, calibration
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* will time out, returning 0.
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*/
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ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
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if (slow_clk == SLOW_CLK_32K_XTAL) {
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rtc_clk_32k_enable(true);
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} else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
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rtc_clk_32k_enable_external();
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}
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// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
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if (SLOW_CLK_CAL_CYCLES > 0) {
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cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
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if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) {
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if (retry_32k_xtal-- > 0) {
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continue;
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}
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ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 90 kHz oscillator");
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rtc_slow_freq = RTC_SLOW_FREQ_RTC;
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}
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}
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} else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) {
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rtc_clk_8m_enable(true, true);
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}
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rtc_clk_slow_freq_set(rtc_slow_freq);
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if (SLOW_CLK_CAL_CYCLES > 0) {
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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* Improve calibration routine to wait until the frequency is stable.
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*/
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cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
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} else {
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const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
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cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
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}
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} while (cal_val == 0);
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ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
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esp_clk_slowclk_cal_set(cal_val);
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}
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void rtc_clk_select_rtc_slow_clk(void)
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{
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select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
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}
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/* This function is not exposed as an API at this point.
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* All peripheral clocks are default enabled after chip is powered on.
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* This function disables some peripheral clocks when cpu starts.
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* These peripheral clocks are enabled when the peripherals are initialized
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* and disabled when they are de-initialized.
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*/
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void esp_perip_clk_init(void)
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{
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uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
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uint32_t common_perip_clk1 = 0;
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RESET_REASON rst_reas[1];
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rst_reas[0] = rtc_get_reset_reason(0);
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/* For reason that only reset CPU, do not disable the clocks
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* that have been enabled before reset.
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*/
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if (rst_reas[0] >= TG0WDT_CPU_RESET &&
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rst_reas[0] <= TG0WDT_CPU_RESET &&
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rst_reas[0] != RTCWDT_BROWN_OUT_RESET) {
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common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
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hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG);
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wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
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} else {
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common_perip_clk = DPORT_WDG_CLK_EN |
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DPORT_I2S0_CLK_EN |
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#if CONFIG_ESP_CONSOLE_UART_NUM != 0
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DPORT_UART_CLK_EN |
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#endif
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#if CONFIG_ESP_CONSOLE_UART_NUM != 1
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DPORT_UART1_CLK_EN |
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#endif
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DPORT_USB_CLK_EN |
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DPORT_SPI2_CLK_EN |
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DPORT_I2C_EXT0_CLK_EN |
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DPORT_UHCI0_CLK_EN |
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DPORT_RMT_CLK_EN |
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DPORT_PCNT_CLK_EN |
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DPORT_LEDC_CLK_EN |
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DPORT_TIMERGROUP1_CLK_EN |
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DPORT_SPI3_CLK_EN |
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DPORT_SPI4_CLK_EN |
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DPORT_PWM0_CLK_EN |
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DPORT_CAN_CLK_EN |
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DPORT_PWM1_CLK_EN |
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DPORT_I2S1_CLK_EN |
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DPORT_SPI2_DMA_CLK_EN |
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DPORT_SPI3_DMA_CLK_EN |
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DPORT_PWM2_CLK_EN |
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DPORT_PWM3_CLK_EN;
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common_perip_clk1 = 0;
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hwcrypto_perip_clk = DPORT_CRYPTO_AES_CLK_EN |
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DPORT_CRYPTO_SHA_CLK_EN |
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DPORT_CRYPTO_RSA_CLK_EN;
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wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
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DPORT_WIFI_CLK_BT_EN_M |
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DPORT_WIFI_CLK_UNUSED_BIT5 |
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DPORT_WIFI_CLK_UNUSED_BIT12 |
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DPORT_WIFI_CLK_SDIOSLAVE_EN |
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DPORT_WIFI_CLK_SDIO_HOST_EN |
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DPORT_WIFI_CLK_EMAC_EN;
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}
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//Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
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common_perip_clk |= DPORT_I2S0_CLK_EN |
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#if CONFIG_ESP_CONSOLE_UART_NUM != 0
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DPORT_UART_CLK_EN |
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#endif
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#if CONFIG_ESP_CONSOLE_UART_NUM != 1
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DPORT_UART1_CLK_EN |
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#endif
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DPORT_USB_CLK_EN |
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DPORT_SPI2_CLK_EN |
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DPORT_I2C_EXT0_CLK_EN |
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DPORT_UHCI0_CLK_EN |
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DPORT_RMT_CLK_EN |
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DPORT_UHCI1_CLK_EN |
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DPORT_SPI3_CLK_EN |
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DPORT_SPI4_CLK_EN |
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DPORT_I2C_EXT1_CLK_EN |
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DPORT_I2S1_CLK_EN |
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DPORT_SPI2_DMA_CLK_EN |
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DPORT_SPI3_DMA_CLK_EN;
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common_perip_clk1 = 0;
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/* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
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* the current is not reduced when disable I2S clock.
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*/
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REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
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REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
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/* Disable some peripheral clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, common_perip_clk1);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, common_perip_clk1);
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/* Disable hardware crypto clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
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/* Disable WiFi/BT/SDIO clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
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/* Enable WiFi MAC and POWER clocks */
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DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN);
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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}
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