faaf59ccb3
Recipe: - Add _M and _V for single-bit fields Search: (#define (\w+)\s*(\(BIT\(\d+\)\))) Replace: \1\n#define \2_M \3\n#define \2_V 1 - Add _M and _V for multi-bit fields Search: (#define (\w+)\s*(0x[\dA-Fa-f]+)) Replace: \1\n#define \2_M (\2_V << \2_S)\n#define \2_V \3
42 lines
1.4 KiB
C
42 lines
1.4 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "soc/soc.h"
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/* Some of the RF frontend control registers.
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* PU/PD fields defined here are used in sleep related functions.
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*/
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#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
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#define FE_IQ_EST_FORCE_PU (BIT(5))
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#define FE_IQ_EST_FORCE_PU_M (BIT(5))
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#define FE_IQ_EST_FORCE_PU_V 1
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#define FE_IQ_EST_FORCE_PU_S 5
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#define FE_IQ_EST_FORCE_PD (BIT(4))
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#define FE_IQ_EST_FORCE_PD_M (BIT(4))
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#define FE_IQ_EST_FORCE_PD_V 1
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#define FE_IQ_EST_FORCE_PD_S 4
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#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
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#define FE2_TX_INF_FORCE_PU (BIT(10))
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#define FE2_TX_INF_FORCE_PU_M (BIT(10))
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#define FE2_TX_INF_FORCE_PU_V 1
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#define FE2_TX_INF_FORCE_PU_S 10
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#define FE2_TX_INF_FORCE_PD (BIT(9))
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#define FE2_TX_INF_FORCE_PD_M (BIT(9))
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#define FE2_TX_INF_FORCE_PD_V 1
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#define FE2_TX_INF_FORCE_PD_S 9
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